Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-03-02
2001-02-06
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S629000, C438S638000, C438S639000, C438S643000, C438S648000, C438S653000, C438S656000, C438S666000, C438S669000, C438S685000
Reexamination Certificate
active
06184118
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method of manufacturing the integrated circuit, and more specifically, to a method for preventing the peeling of the tungsten metal in the integrated circuit after the metal-etching process.
BACKGROUND OF THE INVENTION
The manufacture of the integrated circuit is to form devices on a wafer and then the metallic stage of the integrated circuit is achieved. Consequently, the metallic stage is to form the contact holes on the active region of the devices and then deposit the metal layers to be filled into the contact holes.
In the stage of forming the contact holes of the integrated circuit, verniers of the integrated circuit are formed in this stage. The verniers of the integrated circuit are wide trenches on the substrate and are the alignment marks for the photolithography equipment. Please refer to
FIG. 1
, this drawing shows a cross-section's view of a substrate. On the substrate, a metallic structure is formed thereon. Firstly, a substrate
100
is provided. The substrate
100
is a semiconductor. The integrated circuit is manufactured in the substrate
100
and the integrated circuit is a semiconductor device or a logical circuit. Afterwards, a metal layer
110
is formed on the surface of the substrate
100
and an intermetal dielectric layer
120
is deposited on the metal layer
110
. After the deposition, the intermetal dielectric layer
120
is etched back and the contact holes and verniers are then formed in the IMD layer
120
. Also, the contact holes are the metal contact of the metal layer
110
and the verniers are the alignment marks of the integrated circuit for the photolithography stage.
Afterwards, a barrier layer
130
is deposited on the surface of the contact holes, vernier's region and IMD
120
. A tungsten-metal layer is then formed on the surface of the barrier layer
130
and is etched back to remove part of the tungsten metal layer. The plugs
140
of the contact holes and the spacers
145
of the verniers are thus formed. Finally, an aluminum metal layer is formed on the surface and the metallic stage of integrated circuit is finished.
In the above structure, the verniers are the alignment marks for photolithography and the spacers are formed thereon. The tungsten spacers are easily peeled off in the etching stage of the tungsten metal so that the peeling part of the tungsten spacers can be the short between the cells of the integrated circuit.
Currently, the aligning method of the photolithography stages is a calculating procedure, which is to calculate the distances between the verniers. Referring to
FIG. 2
, this drawing shows two groups of the verniers and a top view of the verniers of the integrated circuit. One is vernier
200
and the other one is vernier
210
. The aligning method of photolithography equipment is to calculate the distances between the vernier
200
and vernier
210
. The black lines in
FIG. 2
are gaps in the IMD
120
. Referring to
FIG. 3
, this drawing illustrates the calculation of the alignment. In the aligning procedures, point A and point B are assigned on the vernier
200
, and point C and point D are assigned on the vernier
210
initially. Afterwards the distance between point A and point C, and the distance between point A and point D, the distance between point B and point C, the distance between point B and point D are calculated. The aligning procedure is then finished following the distances checking.
Consequently, the verniers are necessary for manufacturing the integrated circuit. However, since the spacers of the verniers are very thin films. The peeling phenomena of the spacers is often happened after the etching of metal and deposition. Thus, a method of preventing the peeling phenomena is needed.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method for preventing the peeling of the tungsten metal is disclosed. The method is described by using a preferred embodiment. A structure of the integrated circuit is constructed on a substrate. An intermetal-dielectric layer is deposited on the substrate. Contact holes and verniers are in the IMD layer. The contact holes are the metallic contact of the integrated circuit and the verniers are the alignment marks for the photolithography equipment. A barrier layer covers the surface of the contact holes, the wall of the verniers and the top surface of the IMD layer. A tungsten-metal layer is on the barrier layer and is filled into the contact holes so that the plugs of the contacting holes and the spacers of the verniers are formed. In addition, the tungsten-metal layer covers the edges of the verniers. Thus, the extended portion of the tungsten metal is a metal stopper of the integrated circuit and the adhesion between the metal stoppers and the barrier layer is good so that the peeling of the tungsten spacers is prevented by using the metal stoppers.
REFERENCES:
patent: 5534461 (1996-07-01), Kuwajima
patent: 5891513 (1999-04-01), Dubin et al.
patent: 5899738 (1999-05-01), Wu et al.
patent: 5945716 (1999-08-01), Iwasaki et al.
patent: 5958800 (1999-09-01), Yu et al.
patent: 5972793 (1999-10-01), Tseng
patent: 6002182 (1999-12-01), Madurawe
patent: 6008075 (1999-12-01), Lien et al.
Chung Chen-Hui
Wu Bing-Chang
Gurley Lynne A.
Merchant & Gould P.C.
Tsai Jey
United Microelectronics Corp.
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