Interlayer dielectric planarization process

Details Interlayer dielectric planarization process Interlayer dielectric planarization process

1998-06-12

2001-02-06

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S623000, C438S624000, C438S637000, C438S691000, C438S780000

Reexamination Certificate

active

06184159

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates to semiconductor manufacturing processes, and more particularly, to a method for forming an interlayer dielectric.
BACKGROUND OF THE INVENTION
Interlayer and intermetal dielectric layers are commonly used to isolate conducting structures, such as metal layers, from subsequently deposited conducting layers. The term interlayer dielectric layer generally refers to the insulative layer between the semiconductor substrate and the first metal layer. The term intermetal dielectric layer generally refers to the insulative layer between metal layers.
Intermetal dielectric layers are also useful in performing a planarization function. A typical prior art process for forming an intermetal dielectric layer consists of depositing multiple layers of oxide over the underlying metal layer. For example, a layer of silicon dioxide first covers the metal layer, followed by a low dielectric constant (k) material, followed by a second layer of silicon dioxide. The low k material is used because of its ability to minimize the capacitive “RC time delay constant” between metal lines. The multiple layers of oxide are then patterned and etched to form via holes.
However, it is found that this prior art intermetal dielectric suffers from metal ion diffusion. Specifically, for an intermetal dielectric layer, the low k material used exhibits poor thermal conductivity. What is needed is a new method for forming an interlayer dielectric that will enhance thermal conductivity while maintaining a low RC time delay constant.
SUMMARY OF THE INVENTION
A method of forming a planar interlayer dielectric layer over underlying structures is disclosed. The method comprises the steps of: forming a liner oxide layer over the underlying structures; forming a BPSG layer over the liner oxide layer; polishing said BPSG layer; forming a cap oxide layer over the BPSG layer; and forming a nitride barrier layer over the cap oxide layer.


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