Semiconductor device manufacturing: process – With measuring or testing – Electrical characteristic sensed
Reexamination Certificate
2000-08-25
2001-11-06
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
With measuring or testing
Electrical characteristic sensed
C438S011000, C324S765010
Reexamination Certificate
active
06312964
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates generally to testing/evaluation, and particularly, to a circuit, structure and method of testing a semiconductor, such as an integrated circuit.
2. Discussion of the Related Art
Fabrication of semiconductor structures, such as integrated circuits, involves many steps, and it is thus inevitable that variations will occur in one or more of the steps that will cause the final structure to diverge from an ideal design. Specifically, one or more steps may involve transferring patterns of geometric shapes on a mask to a resist covering the surface of the semiconductor wafer. The patterns, as is well known, may define areas of integrated circuit, such as, for example, a contact, a via, bonding pad area, a metal or poly connecting structure, etc. Of course, the resist patterns are not permanent, but are merely a means to replicate in an underlying layer the desired circuit feature. Conventionally, the pattern transfer is completed by an etching process.
Recognizing that variations occur during the fabrication process which inevitably limit the minimum feature dimension that can be formed on a semiconductor wafer, it is desirable to determine the extent to which the dimensions, as formed on the semiconductor wafer, deviate from an ideal dimension (i.e., so-called “process bias”). Further, as device geometries continue to shrink, it has become more difficult to measure to the absolute value of the minimum feature dimension (i.e., so called “process resolution”). This and related parameters are important since those dimensions affect yield and speed. As another example, an end-of-line determination of process bias may provide the basis for a go no-go (“scrap”) decision concerning the part. That is, too much deviation may cause the part not to operate as desired. Process bias and process resolution arc related. Specifically, determining that a particular feature having a minimum dimension did not form on the semiconductor wafer means both that the process resolution is less than the feature dimension, and, that the process has deviated by at least the minimum feature dimension from the ideal (“process bias”).
One approach taken in the art provides for a visual determination of process bias/resolution. Specifically, a mask used for patterning certain circuit features also includes a test pattern of progressively narrowing width rectangles stacked one above another and collectively positioned adjacent a reference structure (e.g., which may be a “stack” of a plurality of diamond-shaped features). Alternately, right triangles may be used in lieu of rectangles. After the test structure has been “printed” (i.e., photo/etch), a fabrication operator visually identifies the narrowest rectangle that was actually printed. The width of the largest width rectangle that was not formed is used to provide an indication of the process bias/resolution. One disadvantage of this approach is that it is somewhat subjective (i.e, one operator might read a 0.1 &mgr;m bias, while another might see 0.2 &mgr;m. That is, the certainty is less than is desirable. In addition, such approach does not provide the means to evaluate other geometrical features (such as corners), nor integrated structures, such as a combination of layers. The foregoing approach must thus be done for each layer of the semiconductor structure being evaluated.
Another approach in the art seeks to determine the amount of process bias through the generation of an electrical signal, and includes the formation of a test structure on the wafer. The test structure includes a wide electrically conductive rectangle adjoining a narrow electrically conductive rectangle. By impressing a voltage across the test structure, a current flows through both the wide and narrow rectangles. By equating the sheet resistance for each rectangle, a delta width (&Dgr;W) may be derived. The &Dgr;W which provides an indication of the process bias. A disadvantage of this approach is that is requires several pads, including a power supply pad and ground pad. In addition, the electrical tests derives only single delta width; however, the wider conductive rectangle (commonly polycrystalline silicon) may have a different photo/etch bias relative to the narrow rectangle. Thus, the &Dgr;W obtained is really a compromise value. Also, as was the case with the visual test structure, sharp corners or other geometrical features are not monitored for process bias.
There is thus a need to provide an improved test circuit/structure and method that minimizes or eliminates one or more of the problems as set forth above.
SUMMARY OF THE INVENTION
According to one aspect of the present invention, a layout structure for testing an integrated circuit fabricated according to a process is provided. The layout structure includes a plurality of branch structures. A first branch structure has a first feature that is present (i.e., formed) when a process bias supports fabrication of a first predetermined dimension. The first feature is absent (not formed) otherwise. A second branch structure is spaced apart from and adjacent to the first branch structure and has a second feature that is present when the process bias supports fabrication of a second predetermined dimension. The second feature is absent otherwise. In addition, the second predetermined dimension is larger than the first predetermined dimension. The absence of at least one of the first or second features provides an indication of the magnitude of the process bias. The foregoing layout structure provides the means for visually determining the process bias/resolution.
In another aspect of the invention, a device for testing an integrated circuit fabricated according to a process is provided and which includes two major portions. The first major portion comprises a layout structure including a plurality of branch structures as described above. Each branch has a first end and a second end. The plurality of second ends are connected to a common node. The second major portion includes means coupled to the first ends and the common node for generating a process bias signal indicative of a process bias associated with the process. Through the foregoing, an electrical test is provided to determine the extent of the process bias.
In a preferred embodiment, each branch structure includes a respective feature having a predetermined dimension. The respective predetermined dimensions of the branch structures increase progressively. Each feature is present (formed), when a process bias supports fabrication of the respective predetermined dimension. Such feature, when present, is electrically conductive, thus forming an electrical connection between the respective first end and the common node. When the feature is absent the branch structure presents an electrical “Copcn” circuit between the respective first end and common node. The generating means is configured to electrically bias each of the plurality of branch structures. The absence of one or more of the above-mentioned features inhibits or impedes current flow through the branch. The branch currents that do flow are summed at the common node to provide said process bias signal. In alternative embodiments, the features include a variety of alternative geometries, such as a right-angled comer, a contact, a via, as well as other well known features.
In a third aspect according to the present invention, a method for testing an integrated circuit is provided. The integrated circuit includes a layout structure having a plurality of branch structures. The method includes three basic steps. First, generating a control current using an input reference signal. The second step involves establishing a respective branch current through certain ones of the branch structures when a process bias supports fabrication of the respective features (each having their own minimum dimension associated therewith) Finally, the third step involves generating, using the branch currents, an output signal indicative of the process bias obtained dur
Cypress Semiconductor Corp.
Fourson George
Maiorana P.C. Christopher P.
Pham Thanh V
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