Flexible and programmable BIST engine for on-chip memory...

Details Flexible and programmable BIST engine for on-chip memory... Flexible and programmable BIST engine for on-chip memory...

1998-10-30

2001-11-20

Nguyen, Than (Department: 2187)

Electrical computers and digital processing systems: memory

Address formation

Generating a particular pattern/sequence of addresses

C711S218000, C711S219000, C711S101000, C711S105000, C714S006130, C714S030000, C714S738000, C714S738000

Reexamination Certificate

active

06321320

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to testing of memory arrays and, more particularly, to an improved, programmable BIST engine capable of testing and monitoring on-chip memory arrays of an integrated circuit device.
BACKGROUND OF THE INVENTION
As memory arrays have become faster and smaller, the trend has been to place such high-speed arrays on-chip. Consider, for instance, computer systems. Until quite recently, memory, an integral part of any computer system, has been located on integrated circuit (IC) devices separate from the central processing unit (CPU) of the computer system. Communication between the CPU and separate memory devices was accomplished by porting the inputs and outputs of the memory arrays to package pins of the memory devices to the CPA via address and data busses. As IC fabrication technology has evolved to the sub-micron level, as evidenced by devices fabricated using a 0.25-micron or even smaller fabrication process, it has become possible to place large memory arrays, such as random access memories (RAMs), static random access memories (SRAMs), and cache RAMs, entirely on-chip with other circuitry, such as a CPU. On-chip memory arrays provide the advantage of direct communication with the CPU without the need for I/Os to external pins.
In spite of the advantages of placing memory arrays on-chip, there are concerns with how to accomplish testing of such on-chip arrays. On-chip memory arrays, which may account for a large portion, even a majority, of the total die area of a chip, are much harder to control and observe than their discrete predecessors, making it difficult to use traditional external tester equipment and hardware to test, screen, characterize, and monitor on-chip arrays. Visibility into how on-chip memory arrays function is severely limited by the placement of the array-chip interface, such as the interface between a memory array and a CPU core of a microprocessor chip, for instance, on-chip.
Prior methodologies for testing on-chip memory arrays include both Built-In-Self-Test (BIST) and Direct Access Testing (DAT). DAT involves porting the memory array I/Os off the chip in order to engage in direct testing of the array, in a manner similar to testing a discrete memory array device. An example of a prior art DAT implementation
10
is shown in FIG.
1
. In this figure, the chip is shown as a microprocessor
20
having on-chip memory array
22
, multiplexers (mux)
24
and
28
, and central processing unit (CPU) core
26
. Data is provided to memory array
22
from either high-performance tester hardware that is external to the microprocessor and capable of providing address and data pattern sequences
56
at high speed and large bandwidth for at-speed testing or directly from the CPU core
26
. Datapath control of the memory array
22
is therefore provided by multiplexer
24
that provides information
36
to memory array
22
upon selecting information
38
from CPU core
26
or information
42
from the bus interface
30
,
50
or
32
,
52
. Multiplexers
24
and
28
bus interface
34
, and portions of
40
,
42
represent special DAT hardware and signals in the memory array datapath. As shown in
FIG. 1
, DAT I/O interface is provided through bus interface
32
and shared DAT/CPU high-speed chip I/O
52
or, optionally, as indicated by the dashed lines, through DAT I/O interface
34
comprised of bus interface
30
and dedicated DAT high-speed chip I/O
50
. Multiplexer
28
chooses information from either bus
40
or bus
46
to present to bus interface
32
via bus
48
, as shown. Shared DAT/CPU I/O bus
52
is a microprocessor system bus, such as a cache system bus, that is already available. Data from memory array
22
is provided to CPU core
26
and to either bus interface
30
or
32
via cache address and data busses
40
, as shown.
The DAT solution provides the power and flexibility of today's testing equipment but requires more expensive and complex external test support, high-speed I/O for at-speed testing, and additional circuitry and busses than would otherwise be available on the chip in order to properly test and characterize the arrays. For instance, a large memory array that resides on a microprocessor chip, such as a large double- or quad-word accessible cache, would require a large number of external I/O pins or pads of the chip. Additionally, DAT methodologies typically rely upon additional core VLSI datapaths and are thus more dependent on the non-array VLSI.
DAT is also severely challenged by today's high-speed on-chip memory arrays, with frequencies of up to 1 GHz, which typically are much faster than currently available tester technology. A large amount of data must often be presented to the cache of a microprocessor at high speeds, for instance, in order to achieve acceptable fault coverage of the memory. Due to this growing speed discrepancy between on-chip memory arrays and currently available external tester equipment used to test them, the DAT methodology is often no longer capable of testing on-chip memory arrays at speed; it is often necessary to test each array on the chip sequentially or with common test vectors, such as array address and data pattern sequences. Moreover, even as external test equipment can be expected to become faster, memory arrays will themselves also become faster so that this speed discrepancy will continue to be a problem in the future.
BIST differs from DAT in that it essentially integrates the test vector generation provided by the external tester equipment of DAT on-chip. Referring to
FIG. 2
, a BIST implementation is illustrated. BIST moves the test vector generation on-chip microprocessor
20
inside BIST block
64
so that less hardware is required of the BIST implementation than a DAT implementation. Multiplexer
62
, BIST block
64
, portions of bus
40
, and associated address/data bus
68
represent special BIST hardware in the memory datapath. Previous BIST solutions predominantly hard-wired the test vector generation within BIST block
64
to render only limited, fixed test functionality. In order to provide independent, although restricted, access to just the memory array(s)
22
, as opposed to accessing the entire chip
20
, BIST operation and extraction of test results are typically accomplished through IEEE Standard 1149.1 Joint Test Action Group (JTAG) boundary scan Test Access Port (TAP).
What is lacking in the prior art, therefore, is the ability to directly access, test, and monitor on-chip memory arrays in a flexible, thorough manner. Flexibility in test vector generation is particularly essential for testing large, on-chip arrays because it is often impossible to accurately predict critical sensitivities of such arrays. Whether an array passes or fails a given test is dependent upon many interrelated factors, including the voltage to which the array is subjected, the testing temperature, the fabrication process of the array, and the frequency or frequencies at which the array is tested. Large, high-density memory arrays are also notoriously susceptible to various electrical and coupling effects, such as cell-to-cell coupling, bitline coupling, and ground bounce, that may cause logic and timing failures of the array. Moreover, the large number of sub-micron transistors of large, high-density arrays have known possible manufacturing defects, such as particle contamination, missing p-wells, and open/short conditions, for which the arrays must be tested.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to be able to test large, on-chip memory arrays of an integrated circuit chip device in a flexible and through manner.
It is further an object of the present invention that such on-chip memory arrays be able to be easily accessed and monitored.
Therefore, according to the present invention, a structure and methodology of the present invention satisfies these objectives by providing programmable, at-speed on-chip testing, access, and monitoring of one or more on-chip memory arrays. A BIST engine

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