Method and apparatus for efficiently testing RAMBUS memory...

Details Method and apparatus for efficiently testing RAMBUS memory... Method and apparatus for efficiently testing RAMBUS memory...

2000-11-07

2001-11-06

Fears, Terrell W. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S200000, C365S189020, C365S230020

Reexamination Certificate

active

06314036

ABSTRACT:

TECHNICAL FIELD
The present invention relates to memory devices, and more particularly, to a method and apparatus for efficiently performing “core noise” tests on RAMBUS memory devices.
BACKGROUND OF THE INVENTION
Memory devices, such as dynamic random access memories (“DRAMs”), are in common use in computer systems and a wide variety of other electronic products. To insure reliability, DRAMs, are thoroughly tested at several phases of the manufacturing process. For example, DRAMs are tested in die form, i.e., when they are still part of a wafer, and they are tested again after they have been packaged. The large volume of DRAMs that must be tested in a production environment necessitate that testing be performed utilizing automatic test equipment. However, to minimize the cost of testing and to maximize testing throughput, it is important to test DRAMs as quickly as possible. In the past, the rate at which DRAMs can be tested has been increased by compressing the data written to and read from DRAMs. Using data compression, data applied to the DRAM is written to several memory cells, either simultaneously or sequentially in a single memory access cycle. Compressed data is then read from the DRAM by simultaneously coupling data bits from several memory cells to a logic circuit that provides an indication of whether the data read from the memory cells corresponds to the data written to the memory cells. Data compression can markedly reduce the time required to test a DRAM, with the reduction being roughly proportional to the degree of compression. Data compression techniques have been used with a variety of DRAMs, including asynchronous DRAMs and synchronous DRAMs.
Recently, a high-speed packetized memory device, known as a RAMBUS DRAM or “RDRAM”, has been proposed for use in computer systems. The interface to an RDRAM
10
is shown in the block diagram of FIG.
1
. The RDRAM
10
is coupled to first and second 9-bit time-multiplexed data/address buses
12
,
14
. Each of the buses
12
,
14
can couple either an address to the RDRAM
10
or data to or from the RDRAM
10
. Within the RDRAM
10
, the data/address buses
12
,
14
are coupled to a multiplexer
16
that is controlled by appropriate circuitry (not shown) to couple any of the buses
12
,
14
to the either an internal address bus
18
or an internal data bus
20
.
The RDRAM
10
is also coupled to an 8-bit command bus RQ<7:0> that receives command packets for controlling the operation of the RDRAM
10
. One of these lines, RQ<0>, receives a TestBSENSE signal during a core noise test described below. This TestBSENSE signal is coupled through two inverters
22
a,b
to provide an internal BSENSE_in signal and a row address latch RADR_L signal. The RADR_L signal is applied to a Row Address Latch Circuit
26
that latches a row address applied to the RDRAM
10
. The BSENSE_in signal is applied to a Row Sense Control Circuit
28
that senses a row of memory cells corresponding to the latched row address.
Finally, the RDRAM
10
is coupled to a plurality of control and status lines, including a command “CMD” line, a serial clock “SCK” line, and a pair of serial input/output “SIO<1:0> lines. The SIO lines receive serial data on each transition of the serial clock SCK, such as such as control bits that are loaded into internal control registers, including a test option (“TO”) register
24
. The RDRAM
10
is, of course, also coupled to various power and ground lines, but these have been omitted for purposes of brevity.
It will be understood that the RDRAM
10
contains a large amount of circuitry in addition to the multiplexer
16
and the TO register
24
. However, this other circuitry has been omitted in the interests of brevity and clarity since such circuitry is conventional in RDRAMs.
The RDRAM
10
illustrated in
FIG. 1
includes internal circuitry specifically adapted to facilitate testing. One of these test modes, known as the “DA Mode”, can be entered by setting a bit in a register either using the serial SIO port or issuing a command CMD through the command bus RQ<0:7>. Using these test modes, known data can be written to the RDRAM
10
and then read to verify the correct operation of the RDRAM
10
during production and thereafter. Another test, known as the core noise test, tests the RDRAM
10
under what may be considered “worst-case” conditions. In the core noise test, three events occur simultaneously, namely one of the memory banks (not shown) of the RDRAM
10
is precharged, data are written to or read from a memory location in the RDRAM
10
, and a row of memory cells in a memory bank is “sensed,” i.e., the memory cells are coupled to respective digit lines and their respective sense amplifiers respond thereto. Under these circumstances, it is possible for signals on various lines in the RDRAM
10
to be coupled to each other. The core noise test is selected by setting a core noise bit in the TO register
24
(
FIG. 1
) when it is programmed as described above. Once the TO register
24
has been programmed to perform a core noise test, the core noise option is alternately enabled and disabled by toggling the CMD signal line, which is coupled to the TO register
24
.
In the DA test mode, the signals coupled to the lines and buses connected to the RDRAM
10
are given by the following table:
TABLE 1
DQA<0>
DQ/Address
DQA<1>
DQ/Address
DQA<2>
DQ/Address
DQA<3>
DQ/Address
DQA<4>
DQ/Address
DQA<5>
DQ/Address
DQA<6>
DQ/Address
DQA<7>
DQ/Address
DQA<8>
DQ/Address
DQB<0>
DQ/Address
DQB<1>
DQ/Address
DQB<2>
DQ/Address
DQB<3>
DQ/Address
DQB<4>
DQ/Address
DQB<5>
DQ/Address
DQB<6>
DQ/Address
DQB<7>
DQ/Address
DQB<8>
DQ/Address
RQ<0>
TestBSENSE
RQ<1>
TestPRECH
RQ<2>
TestWRITE
RQ<3>
TestCOLLAT
RQ<4>
TestCOLCYC
RQ<5>
TestDSTB
RQ<6>
TestBLOCKD
RQ<7>
TestBLKSEL
CFM
TestCLKW
CFMN
VCC/2
CTM
TestCLKR
CTMN
VCC/2
SCK
SCK
CMD
CMD
SIO<0>
SIO<0>
SIO<1>
SIO<1>
The signal interface to the RDRAM
10
for the core noise test will now be explained with reference to the timing diagram of FIG.
2
. Although many of the signals indicated above are used in various DA Mode tests, only the signals used in the DA Mode core noise test are illustrated in FIG.
2
. Prior to time t
1
, a five-bit bank address PBSEL<4:0> is placed on one of the DQ/Address bus lines
11
-
16
. At time t
1
, the precharge signal TestPRECH applied to the RQ<1> line transitions high. The TestPRECH signal is a control signal that causes the RDRAM
10
to latch an address present on the DQ/Address bus lines
11
-
16
and precharge a bank of memory cells designated by the latched address. Thus, at time t
1
, the bank designated by the PBSEL<4:0> bank address is precharged.
Prior to time t
2
, a 5-bit bank address SBSEL<4:0> is again placed on lines
11
-
16
of the DQ/Address bus, and an 11-bit row address RADR<10:0> is again placed on lines
0
-
10
of the DQ/Address bus. The bank address SBSEL<4:0> and the row address RADR<10:0> correspond to a bank and row, respectively, of memory cells that are to be sensed. When the row of memory cells is sensed, each memory cell in the row is coupled to a respective digit line, a complementary pair of which is provided for each column, and a sense amplifier coupled to each complementary pair of digit lines responds thereto. Sensing a row is, of course, a precursor to reading data from selective columns of memory cells in that row
At time t
2
, a TestBSENSE signal applied to the RQ<0> line transitions low. The TestBSENSE signal is a control signal that causes the RDRAM
10
to latch a row and bank address present on lines
0
-
10
and
11
-
16
, respectively, of the DQ/Address bus and sense a row of memory cells in the bank corresponding to the latched row and bank address. Thus, at time t
2
, the row designated by RADR<10:0> in the bank designated by SBSEL<4:0> is sen

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