Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-03-22

2001-10-09

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Serial read/write

C365S219000, C365S201000, C714S718000

Reexamination Certificate

active

06301182

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly to a semiconductor memory device that comprises one or a plurality of parallel semiconductor memories which simultaneously input or output data with a plurality of bits, and a controller which serves to perform a parallel/serial conversion.
2. Description of the Related Art
Conventionally, a small-sized memory card usually has a bus width the same as or several times wider than a memory (memories) provided on the memory card does (do). Mostly, the memory card simultaneously inputs and outputs data with a plurality of bits, that is, the memory card performs a parallel operation with respect to the inputting/outputting of the data.
FIG. 1
shows an example of the conventional parallel memory card. As shown in this diagram, the conventional parallel memory card comprises a memory
101
and a printed substrate
102
on which the memory
101
is provided.
The memory
101
has a plurality of data inputting-and-outputting terminals D
1
through Dn and a control terminal CTRL consisting of a plurality of control signals of the memory
101
, for example, consisting of a clock signal, a data-direction-determining signal. The printed substrate
102
has a plurality of data inputting-and-outputting terminals
104
-
1
through
104
-n and a control terminal
103
consisting of a plurality of control signals of the printed substrate
102
.
The plurality of data inputting-and-outputting terminals
104
-
1
through
104
-n are coupled to the plurality of data inputting-and-outputting terminals D
1
through Dn, respectively. The control terminal CTRL of the memory
101
is coupled to the control terminal
103
of the printed substrate
102
.
A host reads/writes data from/into the memory
101
via the data inputting-and-outputting terminals
104
-
1
through
104
-n and the control terminal
103
.
In recent years, with increasing demand for miniaturization of the memory card, the memory cards have been downsized more and more. In order to support this situation, a memory card that operates serially is provided. Such a serial memory card comprises a memory operating parallel and a controller serving to perform a parallel/serial conversion. Since the serial memory card communicates serially with the host, the number of the memory card can be reduced and as a result the memory card can be further downsized.
FIG. 2
is a diagram showing an example of the conventional memory card operating serially.
As can be seen from
FIG. 2
, the serial memory card comprises the memory
101
, the printed substrate
102
and a controller
201
.
The controller
201
includes a parallel/serial conversion circuit
202
and an input-and-output control circuit
203
. The parallel/serial conversion circuit
202
has a plurality of parallel terminals coupled to the respective data inputting-and-outputting terminals D
1
through Dn. Also, The parallel/serial conversion circuit
202
has a serial terminal coupled to a serial terminal
205
of the printed substrate
102
.
The host sends a control signal
204
to the control terminal CTRL of the memory
101
via the input-and-output control circuit
203
of the controller
202
. Also, the host writes/reads data into/from the memory
101
installed on the memory card according to a serial control protocol of the controller
201
.
However, in a case of a test for the serial memory card in production thereof, the test has to be performed by serially writing/reading data into/from the serial memory card as previously described. This case brings about a problem that test time is increased and as a result test cost is increased as well, because if the serial memory card having a memory with a data width of 8 bits, the test time thereof is 8 times as long as that of a parallel memory card having the same memory.
SUMMARY OF THE INVENTION
It is a general object of the present invention to provide a semiconductor memory, in which the above problem can be eliminated and for which test time can be reduced.
Another and a more specific object of the present invention is to provide a semiconductor memory, said voltage raising circuit comprising:
a plurality of input/output parallel terminals for inputting/outputting test data.
Still another object of the present invention is to provide a semiconductor memory comprising:
a memory having a plurality of input/output terminals for inputting/outputting parallel data;
a parallel/serial conversion circuit connected to said parallel terminals of said memory so as to perform parallel/serial conversion and input/output serial data;
a plurality of test terminals connected to said parallel terminals of said memory, respectively; and
a switch control circuit arranged between said parallel terminals of said memory and said parallel/serial conversion circuit, for switching said parallel/serial conversion circuit off.
Still another object of the present invention is to provide a semiconductor memory comprising:
a memory having a plurality of input/output terminals for inputting/outputting parallel data;
a parallel/serial conversion circuit connected to said parallel terminals of said memory so as to perform parallel/serial conversion and input/output serial data;
a plurality of test terminals; and
a switch control circuit arranged between said parallel terminals of said memory and said parallel/serial conversion circuit, for switching said parallel/serial conversion circuit off so as to input/output data between said test terminals and said memory, or switching said parallel/serial conversion circuit on so as to input/output data between said memory and said parallel/serial conversion circuit.
Other objects, features and advantages of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings.


REFERENCES:
patent: 5299432 (1994-04-01), Nakae et al.
patent: 5506804 (1996-04-01), Yanagisawa et al.
patent: 5862146 (1999-01-01), Chen et al.
patent: 61-144800 (1986-07-01), None
patent: 402057988A (1990-02-01), None
patent: 02082174 (1990-03-01), None
patent: 411014709 (1999-01-01), None
patent: WO 98/41990 (1998-09-01), None
European Search Report dated Feb. 8, 2001.

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