Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1999-06-17
2001-10-09
Lebentritt, Michael S. (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S152000, C438S166000, C438S308000
Reexamination Certificate
active
06300174
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal panel and related method, and more particularly to a liquid crystal panel in which a thin film pixel driving transistors and thin film driver circuit transistors are integrated on a panel in a single process.
Large area and high resolution active matrix liquid crystal displays (AMLCD) include thin film transistors (TFTs) for driving individual pixels of the display pixels. TFTs are also incorporated into driver circuits for applying signals to gate bus lines and data bus lines coupled to the pixel driving TFTs of the display.
Generally, the driver circuit unit can be an integrated circuit attached to an outer portion of the substrate of the liquid crystal panel, and the driver circuit TFTs formed on the liquid crystal panel. Typically, the complementary metal oxide semiconductor TFTs (CMOS TFTs) with high field effect mobility are used in the driver circuits attached to the liquid crystal panel. Since this type of CMOS TFT consists of polysilicon (p-Si), the switching speed is much higher than that of amorphous silicon (a-Si). Further, because the driver circuit TFT and the pixel driving TFT are fabricated at the same time, the fabrication cost can be decreased.
FIGS. 1
a
-
1
h
illustrate various steps of the conventional method of fabricating a typical liquid crystal panel including TFT driver circuits. For illustrative purposes in
FIGS. 1
a
-
1
h
, the driver circuit unit is shown divided into parts A and B.
As shown in
FIG. 1
a
, a buffer layer
3
is first formed on the substrate
1
and then patterned a-Si semiconductor layers
4
a
,
4
b
and
4
c
are formed on the pixel and driver circuit portions. Semiconductor layer
4
a
corresponds to a transistor driving a single pixel and semiconductor layers
4
b
and
4
c
represent NMOS and PMOS TFTs formed on the driver circuit region.
As shown in
FIG. 1
b
, an insulating layer
5
such as SiO
2
and SiNx, a metal layer
6
such as Al, Al alloy, and Cr, and a photoresist
20
a
are successively formed on buffer layer
3
. The insulating layer
5
and the metal layer
6
are patterned by a photolithography process to form gate insulating layer
5
and gate electrodes
6
a
,
6
b
,
6
c
. Low concentration n
−
ions are introduced into the entire area of the substrate
1
, as shown in
FIG. 1
d
, using gate electrodes
6
a
,
6
b
,
6
c
as masks over semiconductor layers
4
a
,
4
b
,
4
c
. As a result, portions of semiconductor layers
4
a
,
4
b
,
4
c
except those regions covered by gate electrodes
4
a
,
4
b
,
4
c
become doped n
−
layers
12
b
, and the regions under gate electrodes
4
a
,
4
b
,
4
c
become channel layers
12
a.
Thereafter, photoresist layer
20
b
is deposited over substrate
1
and patterned to shield part B of the driver circuit region; gate electrode
6
a
, part of the activation layer, and an n
−
layer of the pixel region. As shown in
FIG. 1
e
, n
+
ions are introduced into the entire surface of substrate
1
. In the pixel region, the width of photoresist
20
b
is larger than that of the gate electrode. Accordingly, the n
+
ions are implanted into a part of the n
−
layer
12
b
. As a result, n
+
layer
12
c
is formed in semiconductor layers
4
a
and
4
b
of the pixel region and part A of the driver circuit region. Further, the resulting transistor in the pixel region has an LDD structure including n
+
layer
12
c
and n
−
layer
12
b.
After photoresist
20
b
is removed, another photoresist layer
20
c
is deposited and patterned to shield the pixel region and part A of the driver circuit, as shown in
FIG. 1
f
. P
+
ions are then implanted into substrate
1
, and p
+
region
12
d
are thus formed in part B of the driver circuit. Regions
12
d
are doped with both p
+
and n
−
ions, and are thus counter doped. Since the n
−
ion concentration is approximately 10
16
~10
18
/cm
3
and the p
+
doping is about 10
19
~10
21
/cm
3
, the n
−
layer
12
b
is converted into p
+
layer
12
d
. Photoresist layer
20
c
is then removed.
Thus, the pixel region has TFTs with an LDD structure, including n
+
layer
12
a
and n
−
layer
12
b
, and the driver circuit has NMOS TFTs having n
+
layer
12
c
and PMOS TFTs including p
+
layers
12
d.
A contact hole is next formed in patterned SiNx insulation layer
7
, as shown in
FIG. 1
g
. A metal, such as Al, is then deposited on insulating layer
7
and into the contact hole to form source/drain electrode
8
. Further, indium tin oxide (ITO) is deposited on the insulating layer
7
and source/drain electrode
8
to form a transparent pixel electrode
9
as shown in
FIG. 1
h
. A passivation layer
10
is then provided blanketing the entire surface. In the liquid crystal panel fabricated according to the above described process, the pixel region has TFTs with an LDD structure and the driver circuit unit includes CMOS TFTs.
Although not shown in the figures, passivation layer
10
is patterned to form pad openings to interconnect the driver circuit region with an outer driver circuit attached to an outer portion of the substrate of the liquid crystal panel. Further, an alignment layer is formed on the passivation layer and rubbed mechanically to provide an alignment direction for the liquid crystal material. Further, another substrate is provided facing the above-described substrate, having color filters and a black matrix formed thereon to prevent light leakage.
In the above mentioned process, ten masks are used for patterning: the semiconductor layer, the n
+
implant mask, the gate insulating layer and gate electrodes, the p
+
implant mask, the contact hole, the source/drain electrodes, the transparent electrode, passivation layer pad openings, and black matrix. The conventional process, therefore, is complicated, the yield is reduced, and the fabrication cost is increased.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a liquid crystal panel having a thin film transistor driver circuit and a related manufacturing method in which the black matrix, pixel unit, and a driver circuit unit are fabricated on one panel, so that the fabrication cost can be decreased and the aperture ratio can be improved.
In order to achieve this object, the present invention provides a method comprising the steps of forming the black matrix on a substrate, forming a buffer layer over the substrate, forming semiconductor layers on the buffer layer, doping n
+
ions into the semiconductor layers using a patterned photoresist layer to mask one of the semiconductor layers and a portion of one of the other semiconductor layers of the driver circuit region, and a portion of the semiconductor layer of the pixel region, thus selectively forming n
+
layers in the semiconductor layer of the pixel region and in the driver circuit region.
The method further comprises the steps of: forming a patterned gate insulating layer on the buffer layer and the semiconductor layer, forming a gate electrode on the gate insulating layer, introducing n
−
ions into the semiconductor layer using the gate electrode as a mask, introducing p
+
ions into the semiconductor layer using a photoresist layer as a mask covering the pixel region and selected ones of the layers of the driver circuit region implanted with n
+
ions to form the p
+
layer in other semiconductor layers of the driver circuit, forming an insulating layer having a contact hole, forming a transparent electrode on the insulating layer of the pixel region and into the contact hole.
Since the width of the gate electrode in the pixel region is narrower than that of the gate electrode in the driver circuit region, the n
−
layer is formed between the n
+
layer and the channel region of the semiconductor layer of the pixel region. Accordingly, the pixel region includes thin film transistors having lightly doped drain structures comprising an n
+
lay
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Lebentritt Michael S.
LG Electronics Inc.
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