Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1999-11-09
2001-10-02
Nguyen, Hiep T. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
06298416
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to data processing systems in general and, in particular, to data processing systems having a hierarchial cache memory architecture. Still more particularly, the present invention relates to a method and apparatus for transmitting control signals within a hierarchial cache memory architecture for a data processing system.
2. Description of the Prior Art
A data processing system typically includes a processor coupled to a variety of storage devices arranged in a hierarchial manner. Hardware and/or software can dynamically allocate parts of the storage devices within the hierarchy for addresses deemed most likely to be accessed soon. The type of storage employed in each hierarchical level relative to the processor is normally determined by balancing the requirements for speed, capacity, and cost.
In addition to a main memory, a commonly employed storage device in the hierarchy includes a high-speed memory known as a cache memory. A cache memory speeds the apparent access times of the relatively slower main memory by retaining the instructions and/or data that the processor will most likely access again soon, and making the instructions and/or data available to the processor at a much lower latency. As such, cache memory enables relatively fast access to a subset of instructions and/or data that were recently transferred from the main memory to the processor, and thus improves the overall speed of the data processing system.
A multi-level cache memory hierarchy is a cache memory system consisting of several levels of cache memories, each level having a different size and speed. Typically, the first level cache memory, commonly known as the level one (L1) cache, has the fastest access time and the highest cost per bit relative to the other levels of cache memories. The remaining levels of cache memories, such as level two (L2) caches, level three (L3) caches, etc., have a relatively slower access time but also a relatively lower cost per bit. Typically, each lower cache memory level has a progressively slower access time and a lower per-bit cost. The present disclosure provides a method and apparatus for transmitting control signals between each level of cache memories within a hierarchial cache memory architecture.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the present invention, a cache memory hierarchy includes multiple levels of cache memories, each level may have a different size and speed. In response to a processor request for information, a control command is sent to the cache memory hierarchy. The control command includes multiple control blocks. Beginning at the lowest possible cache level of the cache memory hierarchy, a determination is made whether or not there is a cache hit at a current level of the cache memory hierarchy. In response to a determination that there is not a cache hit at the current level, an abbreviated control command is sent to a lower cache level of the cache memory hierarchy, after a control block that corresponds to the current level is removed from the control command.
All objects, features, and advantages of the present invention will become apparent in the following detailed written description.
REFERENCES:
patent: 5081873 (1992-01-01), Kikuchi et al.
patent: 5802571 (1998-09-01), Konigsburg et al.
patent: 6219751 (2001-04-01), Hodges
Arimilli Lakshminarayana Baba
Arimilli Ravi Kumar
Fields, Jr. James Stephen
Ghai Sanjeev
Reddy Praveen S.
Bracewell & Patterson L.L.P.
International Business Machines - Corporation
Nguyen Hiep T.
Salys Casimer K.
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