Method for producing semiconductor device

Details Method for producing semiconductor device Method for producing semiconductor device

1998-01-22

2001-11-06

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S683000

Reexamination Certificate

active

06313036

ABSTRACT:

This invention relates to a method for manufacturing a semiconductor device and, more particularly, to a method for manufacturing a semiconductor device containing metal suicides.
BACKGROUND OF THE INVENTION
Referring to
FIG. 6
, the method for manufacturing a semiconductor device of this type is explained in the sequence of manufacturing steps.
Referring first to
FIG. 6A
, a device separation area
2
is selectively formed on a semiconductor substrate
1
of silicon (Si) and an N-well region
3
is then formed by ion implantation of phosphorus (P). A gate oxide film
4
and a gate electrode
5
of polysilicon are formed, and a sidewall
6
of an oxide film is formed, on a sidewall of a gate electrode
5
. BF
2
ions are then implanted by ion-implanation with, for example, an acceleration energy of 20 keV and a dosage of 3E15 (3×10
15
)cm
−2
, followed by heat treatment under the conditions of, for example, 1000° C. and 10 seconds in a nitrogen atmosphere for activation to form a p-type source drain region
7
.
Then, as shown in
FIG. 6B
, arsenic (As) is implanted by ion implantation under the conditions of, for example, 30 keV and 3E14 cm
−2
to render the surface of the p-type source-drain region
7
and the gate electrode
5
amorphous.
Then, as shown in
FIG. 6C
, titanium (Ti) is deposited by a sputtering method, followed by heat treatment of, for example, 700° C. for 30 seconds, to form titanium silicide layer
9
on at least the p-type source-drain region
7
and the gate electrode
5
. Non-reacted titanium is then removed using a solution obtained on mixing ammonia, hydrogen peroxide and water at a ratio of ammonia: hydrogen peroxide: water of 1:1:5, followed by heat treatment at 800° C. for 10 seconds to lower the resistance of the titanium silicide layer
9
.
At this time, titanium silicide layer is not formed in the device separation region
2
of the oxide film nor on the surface of the sidewall
6
. In fact, a layer-to-layer insulating film is then formed followed by opening of contact holes and formation of interconnections. These steps, however, are irrelevant to the subject-matter of the present invention and hence are not stated here specifically.
With the above-described conventional manufacturing method, boron (B) contained in the p-type impurity diffusion layer is sucked up by (diffuses into) the titanium silicide layer
9
of a lower concentration during the time the titanium silicide layer
9
is formed on the semiconductor substrate
1
, thus lowering the boron concentration on the surface of the p-type impurity diffusion layer.
The result is that the contact resistance between the titanium silicide layer
9
and the p-type impurity layer is increased to lower the current driving capability of the p-type MOS transistor.
As a conventional method for overcoming this inconvenience, there is proposed in e.g., JP Patent Kokai Publication JP-A-4-150019 a manufacturing method in which the boron concentration at an interface between the p-type impurity diffusion layer and the titanium silicide layer is prohibited from being lowered despite formation of the titanium silicide layer for suppressing the contact resistance between the two layers.
FIGS. 7A
to
7
C show the conventional manufacturing method step-by-step. Referring first to
FIG. 7A
, a device separation region
2
is formed on a semiconductor substrate
1
mainly composed of silicon. Then, after formation of an N well area
3
, boron is implanted by ion implantation into the semiconductor substrate
1
and activated to form a ptype source-drain region
7
near the surface of the semiconductor substrate
1
.
Then as shown in
FIG. 7B
, titanium ions are implanted at an implantation energy of 30 keV and a dosage of 1E17 cm
−2
, using TiCl
4
as an ion source, to implant titanium ions near the surface of the p-type source-drain region
7
.
If titanium ions are implanted in this manner, titanium ions exist between silicon atoms with a content of the p-type impurities. In this state, boron is further ion-implanted at an implantation energy of 20 keV and a dosage of about 1E15 cm
−2
.
Then, thermal annealing is carried out by a lamp annealing method at a level of 400 to 900° C. This leads to reaction between titanium and silicon in a portion of the semiconductor substrate to form titanium silicide
9
, as shown in FIG.
7
C.
On the other hand, titanium silicide is not formed on the oxide film of the device separation region etc. In the process in which titanium is reacted with silicon to titanium silicide, boron in titanium silicide is diffused to outside. Since the silicide layer is approximately 50 nm, whilst the peak of boron concentration is approximately 60 nm in depth. Thus, even if boron in the titanium silicide layer is diffused, the concentration of boron in titanium silicide and silicon is extremely high, so that, even under certain diffusion of boron into titanium silicide by heat application in the subsequent process, the boron concentration in the interface between silicon and titanium silicide is not lowered. Thus, the contact resistance between the titanium silicide layer and p-type impurity diffusion layer can be prohibited from being increased.
SUMMARY OF THE DISCLOSURE
However, the following problem has been encountered during the investigation toward the present invention. The above-described manufacturing method proposed in the JP Patent Publication Kokai JP-A-4-150019 has a drawback that, since titanium has been formed by ion implantation, titanium silicide (TiSi
2
) having an exact composition cannot be formed without difficulties. The sheet resistance of TiS
2
is lowered to 10 ohm/sq or less only if it has a structure of C
54
.
It is only in case where Ti is formed by sputtering and annealed under a most optimum condition that TiSi
2
with this low resistance value can be produced.
The conventional method of forming titanium by the sputtering method and annealing it to form titanium silicide as shown in
FIG. 6
has a drawback that the contact resistance between the titanium silicide layer and the p-type impurity layer is increased resulting in a lower current driving capability of the p-type MOS transistor.
The reason is that boron contained in the p-type impurity diffusion layer is sucked (diffused) up by the titanium silicide layer of a lower concentration at the time of titanium silicide formation thus lowering the boron concentration in the surface portion of the p-type impurity diffusion layer.
In view of the above-described drawback of the conventional method, it is an object of the present invention to provide a novel method for manufacturing a semiconductor device wherein the contact resistance between the titanium silicide layer and the p-type impurity layer can be prevented from being increased to prevent the current driving capability from being lowered to produce a semiconductor device of a higher operating speed.
Other objects of the present invention will become apparent in the entire disclosure.
According to a first aspect of the present invention there is provided a method for manufacturing a semiconductor device including the steps of ion-implanting a first p-type impurity for forming a source-drain, followed by heat-treatment for activating the implanted ions. The method further includes ion-implanting a second p-type impurity, followed by ion-implanting a third impurity for converting the structure of at least a diffusion layer of the source-drain portion into an amorphous state. Thus, titanium silicide (TiSi
2
) is formed as a layer.
According to the present invention, boron is ion-implanted after forming the source-drain region and before forming TiSi
2
. The result is that boron in the diffusion layer ceases to be sucked (diffused) up during TiSi
2
formation to maintain a high boron concentration in silicon in a portion contacted with TiSi
2
to lower the contact resistance resulting in an increased transistor on-current to raise the circuit operating speed.


REFERENCES:
patent: 3874920 (1975-04-01), Chappelow et al.
patent:

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