Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-03-24
2001-12-11
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S595000, C438S421000, C438S669000, C438S672000, C438S353000
Reexamination Certificate
active
06329279
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 89105038, filed Mar. 20, 2000.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a fabrication method for a semiconductor device. More particularly, the present invention relates to a method of fabricating a metal interconnect structure having an outer air spacer between metal interconnects, applicable to multilevel interconnect technologies.
2. Description of Related Art
In order to build an integrated circuit, it is necessary to fabricate many active devices on a single substrate. Initially, each of the devices must be electrically isolated from the others, and specific devices must subsequently be interconnected in the fabrication sequence so as to implement the desired circuit function, such as processing data in a microprocessor.
The data processing capability of the microprocessor has been extended to respond to more powerful and sophisticated program software, while such extension inevitably requires an increase in the operation speed of a metal oxide semiconductor (MOS) device. The operation speed of the MOS device is increased by creating an environment having a low dielectric constant between adjacent metal interconnects in a multi-level interconnect structure, while such environment is essential for reducing a cross-talk error and a capacitance between the metal interconnects. Since air was known to have a very low dielectric constant (about 1), an optimal dielectric constant for reduction of cross-talk and adverse capacitive coupling in polysilicon and metal interconnect, an air gap structure formed between the metal interconnects has been adopted in most interconnect process. As a result, the circuit speed is improved and logical cross-talk errors are avoided.
FIGS. 1A and 1B
are schematic, cross-sectional diagrams illustrating a conventional method of fabricating the air gap structure.
Referring to
FIG. 1A
, a dielectric layer
100
is provided above a device layer (not shown), wherein the dielectric layer
100
has metal plugs
102
formed therein. Metal lines
104
are formed on the dielectric layer
100
to cover the metal plugs
102
. As a result, the metal lines
104
are not in direct contact with the metal layer (not shown) below the dielectric layer
100
, except through the metal plugs
102
in order to prevent an electrical short.
Referring to
FIG. 1B
, an inter-metal dielectric (IMD) layer
106
is formed to cover the metal lines
104
and the dielectric layer
100
by a method, such as plasma enhanced chemical vapor deposition (PECVD). The IMD layer is usually made of material, such as silicon dioxide, due to its low dielectric constant (about 3.9). According to the method taught by such prior art, one skilled in the art would expect to form a void or air gap
108
between two adjacent metal lines
104
, as shown in FIG.
1
B. However, the air gap
108
formed as such, does not effectively reduce the dielectric constant between the metal lines
104
. Moreover, the air gap
108
can only be formed between metal lines
104
that are in a denser distribution. Therefore, other materials, such as hydrogen silsesquioxane (HSQ) which provides a lower dielectric constant (about 2.9-3.0) and offers a better topographical planarity is needed to reduce the dielectric constant between the metal lines
104
in a metal interconnect structure.
However, when HSQ is applied to interconnect technology, particularly for gap filling, it was found that its dielectric constant may become undesirably high as a result of subsequent processing. For example, after the deposition of the silicon oxide layer by PECVD, the dielectric constant of the deposited HSQ layer undesirably increased from about 2.9 to about 3.6. This rise in dielectric constant is believed to be a result of the oxidation of the top surface of the HSQ due to exposure to an oxygen-containing ambient at an elevated temperature. The undesirable increase in the dielectric constant of the HSQ layer adversely impacts the intra-metal capacitance and, therefore circuit speed.
SUMMARY OF THE INVENTION
The invention provides a fabrication method for a metal interconnect structure having outer air spacers between metal interconnects, applicable to multi level interconnect technologies.
As embodied and broadly described herein, the invention provides outer air spacers between adjacent metal interconnects, which outer air spacers are formed using a double spacer technology. The outer air spacers are formed adjacent to the metal line and are delineated by a second spacer, a metal line, and a second dielectric layer on the first dielectric layer.
According to the present invention, a fabrication method for a metal interconnect structure having outer air spacers between metal interconnects is provided. A first dielectric layer is formed on a MOS device layer, wherein the first dielectric layer has a metal plug formed therein. A patterned metal layer is formed on the first dielectric layer to cover the metal plug, and a first spacer is formed on a sidewall of the patterned metal layer. A second spacer is then formed on the first spacer prior to removal of the first spacer, so that an air gap is formed between the second spacer and the sidewall of the patterned metal layer. A second dielectric layer is formed on the first dielectric layer, the patterned metal layer, and the second spacer, while top of the air gap is partially sealed off by a portion of the second dielectric layer to form an outer air spacer.
Since the outer air spacer is formed closely adjacent to the metal line, the dielectric constant between the metal interconnects is significantly reduced, so that the gap between the metal interconnects can be filled with dielectric materials other than silicon dioxide. The outer air spacer formed as described above is also compatible with other dielectric materials to achieve the objective of reducing the dielectric constant. Furthermore, the outer air spacer can be formed on the sidewalls of the metal lines that are located wider apart. Thus, this ensures a uniform reduction of the dielectric constant between the metal interconnects and improves the circuit speed.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5407860 (1995-04-01), Stoltz et al.
patent: 5915182 (1999-06-01), Wu
patent: 6093612 (2000-07-01), Suh
patent: 6228763 (2001-05-01), Lee
Ueda et al, “A Novel Air-Gap Integration Scheme for Multi-level Interconnects using Self-aligned Via Plugs”, VLSI Technology, 1998, Diggest of Technical Paper Symposium Jun. 9, 1998 pp 46-47.*
Togo et al, “A Gate-side Air-gap Structure (GAS) to reduce the Parsitic Capacitance in MOSFET's”, VLSI Technology 1996, Digest of Technical Paper Symposium Jun. 11, 1996 pp 38-39.*
Shieh et al, “Integration and Reliability Issues for Low Capacitance Air-gap Interconnect structures”, Interconnect Technology Conference 1998, the IEEE International, Jun. 1, 1998 pp.125-127.
Bowers Charles
Huang Jiawei
J. C. Patents
Pham Thanhha
United Microelectronics Corp.
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