Techniques for programming programmable logic array devices

Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...

Reexamination Certificate

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C326S093000, C327S270000, C331S057000

Reexamination Certificate

active

06184705

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to programmable logic array devices, and more particularly to techniques for programming such devices.
Illustrative programmable logic array devices requiring programming are shown in Cliff U.S. Pat. No. 5,237,219 and Cliff et al. U.S. Pat. No. 5,434,514. Typically, such devices are “programmed” in order to set them up to thereafter perform desired logic functions. In other words, the programming determines what logic functions the device will perform. The present invention is particularly of interest in connection with programming programmable logic array devices whose programming memory elements are volatile and reprogrammable. For example, such devices typically require reprogramming each time their power supplies are turned on (from having been off). Such devices may also require reprogramming whenever it is desired to change the logic functions they perform, which may occur during certain normal uses of the devices. Because such programming (or reprogramming) may have to be performed relatively frequently, and because the logic devices are generally not usable during programming, it is important to have rapid and efficient programming techniques.
Programmable logic array devices are often designed to be “general purpose” devices. In other words, the programmable logic device is made without any particular end use in mind. It is intended that the customer will use the number of such devices that is appropriate to the customer's application, and that the customer will program those devices in the manner required to enable them to perform the logic required in the customer's application. Because the size and complexity of various customer applications may vary considerably, it would be desirable to have programming techniques that are modular and lend themselves to programming different numbers of devices with programs of different sizes.
In view of the foregoing, it is an object of this invention to provide improved techniques for programming programmable logic array devices.
It is another object of this invention to provide more rapid techniques for programming programmable logic array devices.
It is still another object of this invention to provide programmable logic array device programming techniques which lend themselves to programming any number of such devices with programs of any size or complexity.
SUMMARY OF THE INVENTION
These and other objects of the invention are accomplished in accordance with the principles of the invention by providing programmable logic array devices which can be programmed one after another in any number from programming devices such as serial erasable programmable read only memories (“serial EPROMs”). Any number of such programming devices can be connected to operate serially. Thus any number of logic devices can be programmed from any number of programming devices, making the programming technique highly modular and capable of performing programming tasks of any size and complexity. The logic devices may be equipped with programming register configurations that allow the logic device to receive several programming data streams in parallel, thereby speeding up the transfer of programming data from the programming device(s) to the logic device(s). A programming device may be equipped with a clock signal generating circuit whose operating speed is programmably variable, thereby enabling the programming device(s) to be used to program logic device(s) having different clock rate requirements. Various communications protocols may be used between the programming devices and the logic devices.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detail description of the preferred embodiments.


REFERENCES:
patent: Re. 34363 (1993-08-01), Freeman
patent: 3473160 (1969-10-01), Wahlstrom
patent: 4020469 (1977-04-01), Manning
patent: 4458165 (1984-07-01), Jackson
patent: 4517532 (1985-05-01), Neidorff
patent: 4609986 (1986-09-01), Hartmann et al.
patent: 4617479 (1986-10-01), Hartmann et al.
patent: 4642487 (1987-02-01), Carter
patent: 4677318 (1987-06-01), Veenstra
patent: 4713792 (1987-12-01), Hartmann et al.
patent: 4758745 (1988-07-01), Elgamal et al.
patent: 4774421 (1988-09-01), Hartmann et al.
patent: 4783606 (1988-11-01), Goetting
patent: 4871930 (1989-10-01), Wong et al.
patent: 4879688 (1989-11-01), Turner et al.
patent: 4899067 (1990-02-01), So et al.
patent: 4912342 (1990-03-01), Wong et al.
patent: 4930107 (1990-05-01), Chan et al.
patent: 5017809 (1991-05-01), Turner
patent: 5121006 (1992-06-01), Pedersen
patent: 5200920 (1993-04-01), Norman et al.
patent: 5220214 (1993-06-01), Pedersen
patent: 5237219 (1993-08-01), Cliff
patent: 5256918 (1993-10-01), Suzuki
patent: 5260610 (1993-11-01), Pedersen et al.
patent: 5260611 (1993-11-01), Cliff et al.
patent: 5323069 (1994-06-01), Smith
patent: 5349311 (1994-09-01), Mentzer
patent: 5350954 (1994-09-01), Patel
patent: 5355097 (1994-10-01), Scott et al.
patent: 5369314 (1994-11-01), Patel et al.
patent: 5371422 (1994-12-01), Patel et al.
patent: 5418499 (1995-05-01), Nakao
patent: 5426379 (1995-06-01), Trimberger
patent: 5432388 (1995-07-01), Crafts et al.
patent: 5434514 (1995-07-01), Cliff et al.
patent: 5448205 (1995-09-01), Rothermel
patent: 5450608 (1995-09-01), Steele
patent: 5457408 (1995-10-01), Leung
patent: 5461591 (1995-10-01), Kim et al.
patent: 5465063 (1995-11-01), Fukuda et al.
patent: 5469003 (1995-11-01), Kean
patent: 5490182 (1996-02-01), Arai
patent: 5490909 (1996-02-01), Mulder et al.
patent: 5493239 (1996-02-01), Zlotnick
patent: 5543730 (1996-08-01), Cliff et al.
patent: 5590305 (1996-12-01), Terrill et al.
patent: 5661662 (1997-08-01), Butts et al.
patent: 0253530 A2 (1987-06-01), None
patent: 0528283 A2 (1993-02-01), None
patent: 1185799 (1970-03-01), None
patent: 1444084 (1972-06-01), None
R. C. Minnick, “A Survey of Microcellular Research,” Journal of the Association for Computing Machinery, vol. 14, No. 2, pp. 203-241, Apr. 1967.
S. E. Wahlstrom, “Programmable Logic Arrays—Cheaper by the Millions,” Electronics, Dec. 11, 1967, pp. 90-95.
Recent Developments in Switching Theory, A. Mukhopadhyay, ed., Academic Press, New York, 1971, chapters VI and IX, pp. 229-254 and 369-422.
S.C. Hu, “Cellular Synthesis of Synchronous Sequential Machines,” IEEE Transactions on Computers, Dec. 1972, pp. 1399-1405.
E.W. Page, “Programmable Array Realizations of Sequential Machines,” Doctoral Dissertation, Department of Electrical Engineering, Duke University, 1973.
Microcomputer Interfacing, H.S. Stone, Addison-Wesley Publishing Company, Reading, Massachusetts, 1982, pp. 95-98.

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