Semiconductor device manufacturing: process – Introduction of conductivity modifying dopant into... – Ion implantation of dopant into semiconductor region
Reexamination Certificate
2000-05-09
2001-11-20
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Introduction of conductivity modifying dopant into...
Ion implantation of dopant into semiconductor region
C438S306000, C438S285000, C257S192000
Reexamination Certificate
active
06319799
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to semiconductor transistors, and more particularly the invention relates to a field effect transistor having a heterostructure quantum well as a conducting channel between a source and drain, each comprising a semiconductor alloy and having heterojunctions.
Cost effective scaling has become a major challenge in silicon MOSFET technology. Traditional techniques are starting to fail in reducing certain undesirable physical effects as device dimensions shrink down to the sub-0.1 micron regime. However, bandgap engineering can provide one more degree of freedom in device design. In order to reduce bulk punchthrough and drain-induced barrier lowering (DIBL), a type of heterojunction MOSFET (HJMOSFET) with band offset at the source/drain junctions has been proposed by Hareland, Tasch, and Mazier in “New Structural Approach For Reducing Punchthrough Current in Deep Submicrometer MOSFETs and Extending MOSFETs Scaling”,
IEEE Electronics Letters
, Vol. 29, No. 21, pages 1894-1896, (October 1993), and in “Analysis of a Heterojunction MOSFET Structure For Deep Submicron Scaling”,
Proceedings of the
21
st International Symp. on Compound Semiconductors
, pages 18-22, (September 1994). See also Verheyen et al., “A Vertical Si/Si
1−x
Ge
x
Heterojunction pMOSFET With Reduced DIBL Sensitivity, Using a Novel Gate Dielectric Approach”, 1999
International Symp. On VLSI Technology, System and Applications
, pages 19-22 (1999). In this structure, Bandgap Engineering is performed horizontally to tailor the potential along the channel. Compared to a silicon control device, a HJMOSFET has lower off-state leakage current and a smaller subthreshold swing. However, the drive current in a HJMOSFET is normally 50-60% lower because most of the carriers have to quantum mechanically tunnel through the potential barrier between the source and drain. See also U.S. Pat. No. 5,155,571 which discloses a MOSFET in which source and drain are formed in a silicon substrate with a GeSi channel region therebetween.
SUMMARY OF THE INVENTION
In accordance with the invention, the performance of a MOSFET is improved by incorporating a heterostructure quantum well in the conducting channel in HJMOSFETs. The band offsets between the source/drain and the channel are eliminated while the band offsets between the source/drain and the semiconductor substrate are retained. Thus, Bandgap Engineering is now performed in both the horizontal and vertical dimensions.
More particularly, the high mobility heterojunction transistor in accordance with the invention includes a semiconductor body of one conductivity type, a source region and a drain region of opposite conductivity type formed in the semiconductor body with each of the source and the drain separated from the substrate by a heterojunction. A channel region is provided between the source region and the drain region which comprises an undoped layer of an alloy of the material of the semiconductor body, and a layer of the material of the semiconductor body overlying the undoped layer. A gate electrode is provided between the source and drain regions on an insulating layer formed on the semiconductor layer.
In a preferred embodiment, the source and drain regions are formed in the semiconductor substrate by implanting dopant of the opposite conductivity type and a material in the alloy of the semiconductor material which are annealed to form an alloy of the semiconductor material under the heterostructure quantum well of the channel region. The doped layer of semiconductor material overlying the undoped alloy layer is oxidized to form a gate dielectric on which the gate electrode is formed.
The invention and objects and features thereof will be more readily apparent for the following detailed description and appended claims when taken with the drawings.
REFERENCES:
patent: 4879256 (1989-11-01), Bean et al.
patent: 5155571 (1992-10-01), Wang et al.
patent: 5539214 (1996-07-01), Lynch et al.
patent: 5684737 (1997-11-01), Wang et al.
patent: 5965931 (1999-10-01), Wang et al.
patent: 6190975 (2001-02-01), Kubo et al.
Wolf, S., Tauber R.N.; Silicon Processing for the VLSI Era vol. 1: Process Technology, Lattice Press, Sunset Beach, CA, 1986, pp. 397-398.*
Hareland, S.A. et al., “New structural approach for reducing punchthrough current in deep submicrometre MOSFETs and extending MOSFET scaling,”IEEE Electronics Letters, vol 29, No. 21, pp. 1894-1896. (Oct. 14, 1993).
Hareland, Scott A. et al., “Analysis of a Heterojunction MOSFET Structure for Deep-Submicron Scaling,” Proceedings of the 21st International Symposium on Compound Semiconductors, 6 pages (Sep. 1994).
Verheyen, P. et al., “A vertical Si/Si1-xGexheterojunction pMOSFET with reduced DIBL sensitivity, using a novel gate dielectric approach,” 1999 International Symposium On VLSI Technology, System and Applications, pp. 19-22 (1999).
Banerjee Sanjay Kumar
Ouyang Qiqing
Tasch, Jr. Al F.
Board of Regents , The University of Texas System
Lattin Christopher
Niebling John F.
Townsend and Townsend / and Crew LLP
Woodward Henry K.
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