Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-10-02
2001-10-30
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S412000
Reexamination Certificate
active
06310376
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor storage device that is electrically erasable and programmable and has non-volatility.
For achieving low power consumption and compacting of electronic equipment, there is needed a semiconductor storage device (EEPROM) that has a high degree of integration and a low power consumption and is electrically erasable and programmable. The semiconductor storage device having the non-volatility has a floating gate between its channel region and gate electrode, and this floating gate is operated as a carrier confining region, the device generally having the following problems.
(i) Since the number of injection and removal of electric charges in the floating gate are limited due to the problem of a reduction in reliability resulting from a hot carrier, there is a limitation in the number of times of write and erase operations.
(ii) A relatively thick insulating film is needed for maintaining the non-volatility. In order to inject an electron or a positive hole into the floating gate by the FOWLER-NORDHEIM tunnel effect through this thick insulating film, a high voltage of not lower than 10 V is required in the present situation. As a result, a hot carrier is generated, and this causes a deterioration of the insulating film by the influence of the formation of a trap and a reaction in the interface due to the hot carrier and alleviation of the hot carrier.
(iii) Since the write and erase operations are executed by a very small current flowing by charging and discharging of the floating gate, the time of charging and discharging is long (on the millisecond order).
Accordingly, a semiconductor storage device that resolves the above problems (i) through (iii) is proposed (Japanese Patent Laid-Open Publication No. HEI 7-302848). In this semiconductor storage device, as shown in
FIG. 5
, a source region
108
and a drain region
110
are formed at a specified interval on a semiconductor substrate
120
, and a floating gate
104
is formed in a region opposite to a channel region
106
between the source and drain regions
108
and
110
via an insulating layer
112
on the semiconductor substrate
120
. Then, the floating gate
104
is covered with an insulating layer
102
, and a control gate
100
is formed on the insulating layer
102
. As shown in
FIG. 6
, the floating gate
104
is provided in the form of a cluster or an island
122
constructed of a semiconductor material having a diameter of 1 nm to 20 nm. Then, the insulating layer
112
located between the channel region
106
and the floating gate
104
is made as thin as possible so as to allow an electron to directly pass through the layer
112
by the tunnel effect, and the energy level of the floating gate
104
is made lower than that of the channel region
106
, thereby preventing the trapped electron from easily escaping.
The following two reference documents describe the fabricating methods of the above floating gate.
(1) A silicon nanocrystals based memory, Sandip Tiwari et al., Appl. Phys. Lett. 68 (10), p1377 (1996)
FIG. 7
shows a schematic diagram of a cross-section of a semiconductor storage device having a floating gate described in the above literature, where a tunnel insulating film
202
having a thickness of 1.1 nm to 1.8 nm is formed on a semiconductor substrate
201
on which a source region
206
and a drain region
207
are formed, and nano-crystals
203
having a diameter of 5 nm are formed at intervals of 5 nm on the tunnel insulating film
202
by a CVD (Chemical Vapor Deposition) system. The density of the nanocrystal
203
is 1×10
12
cm
−2
. Further, a control gate insulating film
204
is formed on the nanocrystals
203
, and SiO
2
is deposited to a thickness of 7 nm on the control gate insulating film
204
, thereby forming a control gate
205
.
(2) Fast and Long Retention-time Nano-Crystal Memory, Hussein I. Hanafi et al., IEEE Trans. Electron Device, Vol. 43, p1553 (1996)
FIGS. 8A through 8C
show a fabricating method of a semiconductor storage device having a floating gate described in the above literature, according to which a thermal oxide film
302
is formed to a thickness of 5 nm to 20 nm on a semiconductor substrate
301
(shown in
FIG. 8A
) and a high dose of ions of silicon Si or germanium Ge is implanted into the thermal oxide film
302
in a supersaturated state (shown in FIG.
8
B). The ion implantation in this case is performed under, for example, the conditions of 5 keV and 5×10
15
cm
−2
. Subsequently, a heat treatment is effected for 30 minutes at a temperature of 950° C. in an atmosphere of nitrogen N
2
, thereby growing nano-crystals
303
of silicon Si or germanium Ge having a diameter of 5 nm in the thermal oxide film
302
. Then, a source region
305
and a drain region
306
are formed at a regular interval on the semiconductor substrate
301
, and a gate electrode
304
is formed on the thermal oxide film
302
oppositely to a region located between the source region
305
and the drain region
306
(shown in FIG.
8
C).
As described in the above literatures (1) and (2), a shift voltage &Dgr;Vth of a threshold voltage Vth when one electron is stored in one nano-crystal is expressed by the following equation:
&Dgr;
Vth=q
(
n
wel
/&egr;
ox
)(
t
cnt1
+(&egr;
OX
/&egr;
si
)
t
well
/2) (equation 1)
where
q: electron charge,
n
well
: nano-crystal density,
&egr;
ox
: dielectric constant of oxide film,
t
cnt1
: film thickness of control gate oxide film,
&egr;
si
: dielectric constant of silicon, and
t
well
: nano-crystal size.
As is apparent from the above equation 1, it can be understood that a variation in device characteristics (&Dgr;Vth) can be reduced by reducing a variation in nano-crystal density n
well
and nano-crystal size t
well
. The film thickness of the tunnel insulating film located between the nano-crystal and the channel is a determinant of the direct tunneling of an electron to the nano-crystal (the probability of tunneling is expressed by a function of the film thickness of the tunnel insulating film), and therefore, a variation in the film thickness of the tunnel insulating film influences the variation in write characteristics. As described above, the above nano-crystal density, nano-crystal size and film thickness of the tunnel insulating film located between the nano-crystal and the channel are the principal parameters to be controlled inherent in the memory.
Concerning the Literature (1)
The semiconductor storage device of the literature (1) utilizes the nano-crystals that happen to be present on the surface of the ground SiO2 film or the nano-crystals that grow in an island shape around random crystalline nuclei occurring in an early stage of CVD. Therefore, neither the nano-crystal density nor the nano-crystal size is controlled, and this leads to the problem that the characteristics vary. On the other hand, in regard to the film thickness of the tunnel insulating film located between the nano-crystals and the channel, because the semiconductor substrate is thermally oxidized in advance, it can be considered that the film thickness can be controlled by the prior art techniques.
Concerning the Literature (2)
In the semiconductor storage device of the literature (2), ions of silicon Si or germanium Ge are implanted into the thermal oxide film
302
and thereafter subjected to heat treatment for the growth of a nano-crystal in the thermal oxide film
302
. However, the implanted ion concentration is distributed in the depthwise direction, for which the ion concentration in the thermal oxide film
302
cannot be uniformed. Therefore, the heat treatment is performed in the state in which the concentration distribution is varied, and therefore, the nano-crystal density in the depthwise direction inside the thermal oxide film
302
also has a distribution. Therefore, it is considered difficult to control the nano-crystal density, the nano-crystal size and the film thickness of the tunnel insulating film located between the nano-crystals an
Fukushima Yasumori
Nakamura Kenta
Ueda Tohru
Nixon & Vanderhye P.C.
Prenty Mark V.
Sharp Kabushiki Kaisha
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