Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-04-08
2001-12-04
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S296000, C257S300000, C257S306000, C257S905000, C257S906000, C257S907000, C257S908000
Reexamination Certificate
active
06326657
ABSTRACT:
This application is based on Japanese patent application HEI 10-281699 filed on Oct. 2, 1998, the whole contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a semiconductor device and its manufacture method, and more particularly to a semiconductor device having memory cells and logic circuits both formed on the same substrate, and its manucture method.
b) Description of the Related Art
In a semiconductor device formed with both dynamic random access memories (DRAM) and logic circuits, a metal silicide film is formed om the source/drain regions and gate electrode of a MISFET in a the logic circuit area in order to improve the performance of logic circuits.
In order to improve the data storage characteristics of memory cells of a semiconductor device such as DRAM, it is desired to reduce junction leak current of source/drain regions. If a metal silicide film is formed on the source/drain regions, the junction leak current increases (refer to The 178-th Meeting, the Electro-chemical Society, pp. 218 to 220). Therefore, the metal silicide film is not formed generally during manufacture processes of DRAM.
In a semiconductor device formed with both DRAM and logic circuits, it is desired that a metal silicide film is not formed in the DRAM area but it is formed only in the logic circuit area.
In the DRAM area, the gate electrode of MISFET constituting a memory cell is generally formed integrally with a word line. In order to lower the resistance of the word line made of polysilicon or the like, it is desired to dope impurities at a high concentration. In the logic circuit area, however, a proper impurity concentration is determined from the threshold value or the like of MISFET. Therefore, the optimum impurity concentrations of the gate electrodes in the memory cell area and logic circuit area are not always coincident.
A precision of an electrostatic capacitance value of a capacitor in an analog circuit in the log circuit area is desired to be made higher. From this reason, generally a three-layer structure of a polysilicon film/a silicon oxide film/a polysilicon film is used. In order to reduce the voltage dependency of a capacitor, it is preferable to make the polysilicon film have a high impurity concentration. In order to suppress an increase in a manufacture cost, it is desired to suppress as much as possible an increase in the number of manufacture processes necessary for forming a polysilicon film of high impurity concentration.
A method is known by which after only the memory cell area is formed, the logic circuit area is formed. If a bit line is disposed under the cell plate which is used as a common electrode of capacitors constituting memory cells, it is necessary that the front end of the bit line protrudes from the boarder of the cell plate in order to electrically connect the bit line and a wiring pattern in the logic circuit area. A process of removing an interlayer insulating film deposited in the logic circuit and a process of patterning a cell plate are therefore required to be executed separately when memory cells are formed.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device and its manufacture method capable of improving the electric characteristics of a logic circuit area while the data storage characteristics of memory cells are maintained good
It is another object of the present invention to provide a semiconductor device formed with both DRAM and memory circuits and its manufacture method, capable of forming capacitors in the logic circuit area while an increase in the number of manufacture processes is suppressed.
It is a further object of the invention to provide a semiconductor device and its manufacture method capable of electrically connecting a bit line in the memory cell area to a wiring pattern in the logic circuit area while an increase in the number of manufacture processes is suppressed when only the memory cell area is formed before the logic circuit area is formed.
According to one aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: preparing a semiconductor substrate having a memory cell area and a logic circuit area defined on a principal surface of the semiconductor substrate; forming a gate insulating film on the principal surface of the semiconductor substrate; forming a silicon film on the gate insulating film; doping impurities into the silicon film to make a region of the silicon film in the memory cell area have a first impurity concentration and to make a region of the silicon film in the logic circuit area have a second impurity concentration lower than the first impurity concentration; patterning the silicon film to leave word lines having the first impurity concentration and serving as gate electrodes in the memory cell area and to leave gate electrodes having the second impurity concentration in the logic circuit area; and forming source/drain regions of MISFET's in a surface layer of the semiconductor substrate by doping impurities into regions on both sides of each word line in the memory cell area and into regions on both sides of each gate electrode in the logic circuit.
Since the impurity concentration of word lines in the memory cell area is relatively high, the resistance of the word line can be lowered. Since the impurity concentration of gate electrodes of MISFET's in the logic circuit area is relatively low, the electrical characteristics of MISFET's can be improved.
According to another aspect of the present invention, there is provided a semiconductor device comprising. a semiconductor substrate having a memory cell area and a logic circuit area defined on a principal surface of the semiconductor substrate; a plurality of memory cells disposed in the memory cell area of the semiconductor substrate, each memory cell including a first MISFET and a capacitor, and a gate electrode of each first MISFET having a first impurity concentration; and a plurality of second MISFET's disposed in the logic circuit area of the semiconductor substrate, each second MISFET having a conductivity type same as a conductivity type of the first MISFET and a gate electrode of each second MISFET having a second impurity concentration lower than the first impurity concentration.
Since the impurity concentration of gate electrodes of MISFET's in the memory cell area is relatively high, the resistance of the word line serving also as the gate electrode can be lowered. Since the impurity concentration of gate electrodes of MISFET's in the logic circuit area is relatively low, the electrical characteristics of MISFET's can be improved.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: preparing a semiconductor substrate having a memory cell area and a logic circuit area defined on a principal surface of the semiconductor substrate; forming an element separation structure made of insulating material in a partial area of the principal surface of the semiconductor substrate to define active regions; forming first gate insulating films in areas of the principal surface of the semiconductor substrate where the element separation structure is not formed; forming a first conductive film covering the element separation structure and the first gate insulating films; removing the first conductive film in the memory cell area; forming a capacitor dielectric film on a surface of the first conductive film; forming a second conductive film on the capacitor dielectric film and on the semiconductor substrate; patterning the second conductive film to leave an upper electrode over the element separation structure and to lave a plurality of word lines serving as gate electrodes in the memory cell area; and patterning the capacitor dielectric film and the first conductive film to leave a lower electrode made of the first conductive
Armstrong Westerman Hattori McLeland & Naughton LLP
Fujitsu Limited
Lee Eddie
Ortiz Edgardo
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