Semiconductor device manufacturing: process – Chemical etching – Liquid phase etching
Reexamination Certificate
2000-08-14
2001-12-11
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Liquid phase etching
C438S749000, C438S750000, C438S751000, C438S754000
Reexamination Certificate
active
06329301
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to improved semiconductor processing technology. More specifically, the present invention relates to an improved process and apparatus for locally removing any desired material from predetermined areas of a silicon wafer in process during the formation of integrated circuits thereon, such as the removal of material from the wafer alignment mark areas of a silicon wafer.
2. State of the Art
The fabrication of integrated circuits on silicon wafers utilizes many differing processes and materials. For instance, photolithographic techniques are used to pattern the various gates on the silicon chip. As sophisticated pattern definition technologies have been used, the geometries of the integrated circuit components have shrunk from the 6 micron size of the late 1970's to the submicron technologies of the late 1980's to the deep submicron regions of the 1990's. Therefore, it has become increasingly important to carefully align the wafer during semiconductor device manufacturing processes. Also, as the size of the features of the integrated circuits has become increasingly smaller and the spacing of the semiconductor devices has decreased on the wafer, of necessity, the size of any predetermined area of the wafer containing any feature or circuit component on the wafer has decreased. For instance, the alignment marks on the wafer used to align the wafer during manufacturing processes and the area surrounding the alignment marks on the wafer have become increasingly smaller.
Due to various constraints in semiconductor device manufacturing processes, it is critical that predetermined areas of the wafer be free of material contamination during the process. As an example, the alignment marks on the wafer should be kept free of contaminants so that the process equipment can easily locate and use such alignment marks. In various semiconductor manufacturing processes, the alignment marks can easily become contaminated or covered with various process materials. In such instances, it is necessary to clean the alignment marks on the wafer before any subsequent processing occurs to ensure proper alignment of the wafer on the process equipment.
As one example of such process problems, after the application of a photoresist material used in a circuit forming process and the subsequent etching of the wafer to form the desired circuit or portion thereof, the alignment marks on the wafer may be covered with photoresist material which must be removed prior to the continued processing of the wafer.
As another example, a chemical mechanical planarization process is the preferred method of planarizing various films and coatings on wafers. However, a chemical mechanical planarization process does not necessarily uniformly remove material from the wafer surface due to either dishing of the polishing pad caused by surface irregularities on the wafer and/or the non-uniform application of the polishing slurry over the wafer surface. Such problems occur, particularly, when using a chemical mechanical planarization process to remove refractory metal films and the like. Since the refractory metal film is not of uniform thickness, the refractory metal film may not be removed in the areas of the wafer where alignment marks are present or other predetermined areas of the wafer. Furthermore, the alignment marks, or other predetermined areas, on the wafer may also be covered with slurry material used in the chemical mechanical planarization process or have residual refractory metal film remain which has not been removed during the chemical mechanical planarization process thereon, thereby obscuring the alignment marks. Therefore, it is desirable to have a method and apparatus for cleaning predetermined areas of the wafer, such as the alignment marks of wafers, after chemical mechanical planarization processes thereon.
As an example of such wafer process problems discussed above, the fabrication of multi-level interconnections in integrated circuits has been facilitated through the use of tungsten, a refractory metal. However, tungsten is difficult to etch selectively because the surface of most tungsten films deposited using chemical vapor deposition techniques is rough and because tungsten and silicon dioxide form volatile fluoride compounds. Due to such problems, it is difficult to selectively etch tungsten to remove the unwanted tungsten that remains on the low areas of the wafer surface, such as those areas where semiconductor devices are being formed, or in predetermined areas of the wafer, such as those areas of the wafer surface where alignment marks exist.
Since a tungsten film covers the surface of semiconductor devices being formed on the wafer surface, the tungsten film must be etched back selectively so that the tungsten film only remains in the vias or contact holes to eliminate the tungsten film in the low areas of the wafer surface. Several methods use either a photoresist or a polyimide sacrificial film to planarize the tungsten film. Using these methods requires the sacrificial film to be highly planarized, followed by an over-etch to clear all of the tungsten film from the low areas of the wafer surface that are present after the planarization of the wafer surface. Since tungsten etching is difficult to control to produce a uniform surface on the wafer, over-etching is often required to insure tungsten removal. However, over-etching can result in recessed tungsten plugs which interconnect the integrated circuitry being formed on the wafer in process, particularly when the wafer is not of uniform thickness. Additionally, over-etching may not remove the tungsten from all low areas of the wafer surface, such as those areas where the alignment marks of the wafer are present or other predetermined areas of the wafer.
In a prior art process, described in U.S. Pat. No. 5,271,798, a method for the selective etching of the alignment mark areas of the wafer is set forth to selectively etch the alignment mark areas of the wafer using a wet etching process which can be controlled and isolated to a specific area of the wafer. In the prior art process, tungsten is selectively etched locally from the alignment marks on the wafer either before or after the chemical mechanical planarization process. The wafers are flat aligned and a tungsten etch solution is introduced through an enclosed etchant dispensing apparatus onto low lying areas of the wafer surface which result from the alignment marks used for aligning various photolithography mask steps. Since the alignment marks are normally a few hundred microns in size and if a large amount of unused silicon area exists around the alignment marks, the alignment area constraints regarding an enclosed etchant dispensing apparatus and wafer are not too severe. Also, when a large amount of unused silicon area exists around the alignment marks, the tungsten plugs in the semiconductor device being formed on the wafer can be easily protected from the wet etch. Either during or after the etch, the etching products are removed and the wafers are cleaned by being rinsed in distilled water.
In U.S. Pat. No. 5,271,798, a method and apparatus is illustrated for the cleaning of alignment marks on a wafer. The apparatus illustrated uses a cylindrical containment apparatus having a seal on the bottom thereof to sealingly engage the area surrounding the alignment mark on a wafer. An etchant is dispensed through the containment apparatus onto the alignment mark on the wafer to etch contaminants therefrom with the etchant being removed from the alignment mark area by a vacuum. Such a prior art method and apparatus require a physical contact seal between the containment apparatus and the wafer area surrounding the alignment mark which may cause damage to the surface of the wafer or surrounding semiconductor devices being formed on the wafer.
However, as discussed previously, with the increasing density of semiconductor devices formed on the wafer surface, the area available for the placement of se
Dobson Todd A.
Gordon Brian F.
Hudson Guy F.
Stroupe Hugh E.
Zahorik Russell C.
Micro)n Technology, Inc.
TraskBritt
Utech Benjamin L.
Vinh Lan
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