Method for forming buried layers with top-side contacts and...

Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate

Reexamination Certificate

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Details

C438S524000

Reexamination Certificate

active

06316336

ABSTRACT:

BACKGROUND AND SUMMARY OF THE INVENTION
The present invention relates to the formation of integrated circuits in semiconductors, and especially to the formation of buried layers in a semiconductor.
Background: Buried Layers in Semiconductor Processing
Buried layers are regions of dopant that are formed beneath the surface of wafers in semiconductor processing technology. Buried layers are most often formed by introducing regions of the desired dopant into the surface of a wafer early in the semiconductor manufacturing sequence and then depositing an additional layer of the semiconductor material over the surface of the entire wafer, thereby “burying” the newly introduced doped region. The process step used to deposit the additional layer of semiconductor material is called epitaxial deposition. Following the epitaxial deposition step, the crystal structure of the deposited material matches the crystal structure of the original wafer. Dopant is added in the deposition step to guarantee that the epitaxial layer has the desired dopant type and range of dopant concentration.
The sequence of forming a buried layer under an epitaxial layer is shown in
FIGS. 2A-2C
.
FIG. 2A
shows a cross section of a semiconductor wafer at the beginning of circuit fabrication, showing only the substrate
200
.
FIG. 2B
shows the same wafer after a doped region
210
, which will become the buried layer, has been formed. After the doped regions
210
is formed, epitaxial layer
220
is grown, and reach-down contacts
230
are implanted or deposited and diffused. The wafer with buried layer
210
′ is seen in FIG.
2
C. The use of epitaxial deposition and a diffused isolation region as shown in
FIG. 2C
allows the formation of regions of semiconductor material that are electrically isolated from each other while being in close physical proximity. The buried layer reduces the resistance of the electrical path that current must flow through in an integrated circuit.
The epitaxial deposition step in the formation of buried layers is a costly step, so alternative methods of forming buried layers have been investigated. One such technique is to use high-energy ion implantation to introduce the buried layer dopant atoms into the semiconductor material at a depth below the surface of the semiconductor. The depth that dopant atoms can be introduced using ion implantation is limited to just a few microns due to the energy required to implant the atoms deeper. The introduction of the high doses of dopant required for some buried layers may also permanently alter the characteristics of the semiconductor material that the dopant atoms pass through during the ion implantation step.
Forming a Buried Layer Without Epitaxy
It is herein disclosed to form buried layers in a semiconductor by first forming trenches in the semiconductor wafer, using conventional lithographic and etching techniques. After formation of a layer of dielectric on the bottom and sides of the trenches, a dopant is introduced into the silicon beneath the trenches. The trenches will be filled, either with a dielectric or a conductor, as desired for the particular layout, then the dopant is caused to diffuse until the regions from the trenches meet and merge, forming a continuous buried layer underneath the surface of the wafer.
The disclosed innovations, in various embodiments, provide one or more of at least the following advantages:
no need to grow epitaxial layers;
less expensive than other methods;
buried layer can be at any depth;
multiple layers can be formed in various configurations;
overlying semiconductor is not altered, as in ion implantation.


REFERENCES:
patent: 3976512 (1976-08-01), De Nora et al.
patent: 4044452 (1977-08-01), Abbas et al.
patent: 5959324 (1999-09-01), Kohyama
patent: 92830455.9 (1994-03-01), None
patent: 58250536 (1983-12-01), None
patent: 04184833 (1992-07-01), None
patent: WO 99/16123 (1997-09-01), None

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