Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-06-03
2001-02-13
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S657000, C438S658000, C438S630000, C438S233000, C438S664000, C438S682000
Reexamination Certificate
active
06187675
ABSTRACT:
TECHNICAL FIELD
This invention relates to MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and more particularly to a method for fabricating a MOSFET gate with relatively thick metal silicide on polysilicon for a gate with low resistivity.
BACKGROUND OF THE INVENTION
Referring to
FIG. 1
, a cross sectional view of a conventional MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
100
includes a drain region
102
, a source region
104
, and a channel region
106
fabricated within a semiconductor substrate
108
, as known to one of ordinary skill in the art of electronics. A gate dielectric
110
is disposed over the channel region
106
of the MOSFET
100
. The MOSFET
100
also includes a gate comprised of polysilicon
112
disposed over the gate dielectric
110
. Spacer structures
113
typically formed of an insulating material surround the gate dielectric
110
and the gate structure over the gate dielectric
110
, as known to one of ordinary skill in the art of electronics.
For making contact to the drain region
102
, the source region
104
, and the polysilicon
112
of the gate, a metal silicide is formed on the drain region
102
, the source region
104
, and the polysilicon
112
of the gate. A drain silicide
114
is formed on the drain region
102
, a source silicide
116
is formed on the source region
104
, and a first metal gate silicide
118
is formed on the polysilicon
112
of the gate of the MOSFET
100
.
For efficiency in fabrication, the drain silicide
114
, the source silicide
116
, and the first metal gate silicide
118
are typically fabricated simultaneously in the prior art. During the fabrication of the silicides, the drain region
102
, the source region
104
, and the polysilicon
112
are exposed, and metal is deposited on those regions. Then, a silicidation anneal is performed, and the drain silicide
114
, the source silicide
116
, and the first metal gate silicide
118
form from a reaction of the deposited metal with silicon during the silicidation anneal.
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
Referring to
FIG. 1
, as the dimensions of the MOSFET
100
are scaled down, the depth of diffusion of the drain region
102
and the source region
104
into the semiconductor substrate
108
and the thickness of the polysilicon
112
of the gate are scaled down. Thus, the depth of the drain silicide
114
and the source silicide
116
and the thickness of the first metal gate silicide
118
are also scaled down during simultaneous fabrication of the drain silicide
114
, the source silicide
116
, and the first metal gate silicide
118
.
However, such scaling down of the thickness of the first metal gate silicide
118
results in higher resistivity of the gate of the MOSFET
100
. Such higher resistivity in turn leads to slower device speed of the MOSFET
100
. Nevertheless, scaling down the dimensions of the MOSFET
100
is also advantageous.
Thus, a method is desired for fabricating a gate with low resistivity within such a MOSFET with scaled down dimensions.
SUMMARY OF THE INVENTION
Accordingly, the present invention is a method for fabricating a gate of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) with the gate having low resistivity. The MOSFET has a drain region, a source region, and a channel region fabricated within a semiconductor substrate, and the MOSFET initially has a gate comprised of a first metal silicide on polysilicon disposed on a gate dielectric over the channel region. Generally, the method of the present invention includes a step of depositing a first dielectric layer over the drain region, the source region, and the gate of the MOSFET. The present invention also includes steps of polishing down the first dielectric layer over the drain region and the source region, and of polishing down the first dielectric layer over the gate until the first metal silicide on the polysilicon or the polysilicon of the gate is exposed. The present invention further includes a step of depositing a metal on the first metal silicide that is exposed or on the polysilicon that is exposed. A silicidation anneal is then performed to react the metal with the polysilicon to form a predetermined thickness of a second metal silicide over a remaining portion of the polysilicon. The predetermined thickness of the second metal silicide is greater than a thickness of the first metal silicide to result in a MOSFET gate with low resistivity. In addition, the present invention includes the step of removing any portion of the metal that is not reacted during the silicidation anneal.
In this manner, the gate of the present invention has low resistivity since a relatively thick layer of the second metal silicide is formed on the remaining portion of the polysilicon. However, with the present invention, the remaining portion of the polysilicon has a sufficient thickness such that a threshold voltage of the MOSFET is not significantly affected by the second metal silicide disposed on top of the remaining portion of the polysilicon. The present invention may be used to particular advantage for fabricating a gate with low resistivity for a MOSFET with scaled down dimensions.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.
REFERENCES:
patent: 4780429 (1988-10-01), Roche et al.
patent: 5731239 (1998-03-01), Wong et al.
patent: 5953612 (1999-09-01), Lin et al.
Yukio Fukuda, Shigeto Kohda, and Yoshitaka Kitano, A New Aluminum Pattern Formation Using Substitution Reaction of Aluminum for Polysilicon and Its Application to MOS Device Fabrication, IEEE Transactions on Electron Devices, vol. Ed-31, No. 6, Jun. 1984, pp. 828-832.
Advanced Micro Devices , Inc.
Berezny Neal
Choi Monica H.
Fahmy Wael
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