Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1998-08-26
2001-02-13
Peikari, B. James (Department: 2752)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S119000, C711S168000, C711S149000
Reexamination Certificate
active
06189073
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed generally to hierarchical cache memory structures.
2. Description of the Background
In a computer, the central processing unit (CPU) executes instructions at a predetermined rate. To obtain the instructions to be executed, or the data which is to be manipulated, the CPU must access a memory which contains the necessary instructions and data. Such memory is typically one of two types. A static random access memory (SRAM) is characterized by operation in one of two mutually-exclusive and self-maintaining states. Each static memory cell typically has an output which reflects a “high” voltage or “low” voltage representative of a logic level “1” or a logic level “0”, respectively.
Another type of memory is the dynamic random access memory (DRAM) which does not have stable states of operation. A DRAM, like an SRAM, can be programmed to store a voltage which represents a logic level “1” or a logic level “0” but requires periodic refreshing to maintain those logic levels for more than a very short period of time. Despite that limitation, DRAMs are frequently used because of the significantly greater packing density which can be obtained, and because of the substantially lower cost associated therewith. Thus, in a computer, it is not unusual to find that the large main memory is comprised of DRAMs.
Because a CPU operating in conjunction with a main memory constructed of DRAMs will operate at a substantially faster speed than such a main memory, a smaller cache memory, typically constructed of SRAMs, is often used to buffer the data and the instructions between the main memory and the CPU. The cache memory is typically managed under hardware control and maintains a copy of certain portions of the information found in the main memory. The information maintained in the cache memory are those instructions and data which the CPU is likely to use. Thus, because the CPU can often find the instructions and data needed in the faster cache memory, the speed at which the CPU can operate is no longer limited to the access time of the main memory.
Despite the use of SRAM cache memory, CPU's still operate faster than instructions and data can be provided thereto. Recently, CPU's have been introduced that have execution cycle times under five nanoseconds, which is below the access time of typical SRAMs. To enable such fast CPU's to operate more efficiently, “on-chip” cache memories provide an additional level of cache memory between the processor and the external SRAM cache memory. The use of such on-board cache memory creates a hierarchical situation between the on-board cache memory and the external cache memory. That hierarchical arrangement allows the CPU to operate more quickly because the data and instructions required by the CPU are likely to be found in one of the cache memories. However, the need still exists to provide memory devices which have faster access times so that external cache memory constructed of SRAMs may allow CPU's to operate as close as possible to their limits.
SUMMARY OF THE INVENTION
The present invention, in its broadest form, is directed to a circuit for internally caching a memory device having a main memory. The circuit is comprised of a cache memory of smaller size than the main memory for storing certain portions of the same data stored in the main memory. A tag memory is provided for mapping the information stored in the cache memory. A logic circuit is in communication with the main memory, the cache memory, and the tag memory for controlling the input of data thereto and output of data therefrom. The cache memory, tag memory, and logic circuit are carried internally in the memory device.
The present invention solves the problem of improving the performance of SRAMs by providing an internally cached SRAM circuit comprised of a main static random access memory array for storing data. A cache static random access memory array of smaller size than the main array is provided for storing certain of the same data that is stored in the main memory. A tag static random access memory array for mapping the information stored in the cache memory is also provided. A logic circuit is in communication with the main memory, the cache memory, and the tag memory for interrogating the tag memory in response to a request for data. The logic circuit retrieves the requested data from either the main memory or the cache memory in response to the results of the interrogation. The logic circuit also inputs the retrieved data to the cache memory while updating the tag memory if the retrieved data is found only in the main memory. Finally, the logic circuit inputs data to both the main memory and the cache memory while updating the tag memory in the event new data is to be stored.
The foregoing cached memory device results in an SRAM with improved performance because the smaller cache memory can respond more quickly than the larger main memory, even though both memory arrays are constructed of static cells. That is because, among other factors, a smaller SRAM has less internal capacitance to overcome and therefore can be read more quickly.
Another aspect of the present invention is that the aforementioned architecture can be used to enable a single-port SRAM to emulate a dual-port device. To implement such an embodiment, a second cache static random access memory array, a second tag static random access memory array, and a second logic circuit in communication with the second cache memory and the second tag memory, are provided. Multiplexers are responsive to one of the logic circuit and the second logic circuit for accessing an input port of the main memory. In that manner, access times are again improved. Furthermore, that concept can be applied to implement more than two ports of access. Those and other advantages and benefits of the present invention will become apparent from the Description Of The Preferred Embodiments hereinbelow.
REFERENCES:
patent: 4724518 (1988-02-01), Steps
patent: 4733352 (1988-03-01), Nakamura et al.
patent: 5130922 (1992-07-01), Liu
patent: 5265235 (1993-11-01), Sindhu et al.
patent: 5287484 (1994-02-01), Nishii et al.
patent: 5289588 (1994-02-01), Song et al.
patent: 5317716 (1994-05-01), Liu
patent: 5329633 (1994-07-01), Lee et al.
patent: 5437022 (1995-07-01), Beardsley et al.
patent: 5477445 (1995-12-01), Weber
patent: 5669009 (1997-09-01), Buktenica et al.
patent: 5689680 (1997-11-01), Whittaker et al.
patent: 5802561 (1998-09-01), Fava et al.
patent: 5809536 (1998-09-01), Young et al.
patent: 5893143 (1999-04-01), Tanaka et al.
Micro)n Technology, Inc.
Peikari B. James
Thorp Reed & Armstrong
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