Method for fabricating metal interconnect structure

Details Method for fabricating metal interconnect structure Method for fabricating metal interconnect structure

1999-03-29

2001-02-13

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S623000, C438S627000, C438S637000, C438S638000, C438S692000

Reexamination Certificate

active

06187661

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88103216, filed Mar. 3, 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a method of fabricating a metal interconnect, and more particularly, to a fabrication method of dual damascene.
2. Description of the Related Art
High-density integrated circuits, such as very large scale integration (VLSI) circuits, are typically formed with two or multiple metal interconnects to serve as three-dimensional wiring line structures to comply with a very high density of devices. A multilevel interconnect structure comprises a first metal wiring layer electrically connecting to a source/drain region in a substrate via a metal plug. The electrical connections between various devices are achieved by the formation of a second or other metal wiring layers. As the integrated density of devices increases, the capacitance effect between metal wires increases. Consequently, the resistance-capacitance time delay (RC delay time) increases, and cross talk between the metal wires become more frequent. The metal wires thus carries a current flow in a slower speed.
In response with the development of the fabrication process of integrated circuits, the resistivity of each of the metal wires and the parasitic capacitance between the metal wires become crucial factors to determine the speed of current flow. To achieve the reduction of the resistivity of metal wires, materials with low resistivity are selected for fabricating the metal wires. The objectivity of reducing the parasitic capacitance can also be achieved by fabricating insulating layers with low dielectric constants between the metal wires.
In a conventional fabrication process, a metal plug is formed in a dielectric layer, followed by forming a metal wiring layer to couple with the metal plug. However, problems of overlay error and process bias frequently occur during photolithography. A dual damascene process has been developed to resolve the problems occurring in the conventional fabrication process, so as to enhance reliability of devices and improve the process performance. The dual damascene thus becomes a popular technique to form a dual damascene structure of insulating layers with low dielectric constants in accordance with highdensity of devices.
FIGS. 1A through 1D
are schematic, cross-sectional views showing a conventional method for fabricating a dual damascene structure.
Referring to
FIG. 1A
, a substrate
100
comprising a transistor is provided. The substrate
100
further comprises a metal wire
102
. An oxide layer
104
and a hard mask
106
are formed on the substrate
100
in sequence. A conventional photolithography and etching process is applied to form an opening
108
within the hard mask layer
106
.
Referring to
FIG. 1B
, an oxide layer
110
is deposited on the hard mask layer
106
to fill the opening
108
.
Referring to
FIG. 1C
, a patterned photo-resist layer
112
is formed on the oxide layer
110
. Using the hard mask layer
106
as an etching stop layer, the oxide layer
110
is etched with the photo-resist layer
112
as a mask. Meanwhile, the oxide layer
104
at a bottom of the opening
108
is also etched to form a dual damascene opening
114
. The photo-resist layer
112
is then stripped using oxygen plasma.
Referring to
FIG. 1D
, a conductive layer
116
is formed to fill the dual damascene opening
114
. A dual damascene structure is thus formed.
As mentioned above, the problem of parasitic capacitance caused by an inter-metal dielectric layer between two metal layers becomes more and more obvious as the integrated density of semiconductor devices grows. Thus, in deep sub-micron semiconductor fabrication process, an inter-metal dielectric layer with a low dielectric constant such as the oxide layer
110
shown in
FIG. 1B
is used to moderate the effect of RC time delay. However, a photo-resist layer is typically made of high molecular material, and the inter-metal dielectric layer with a low dielectric constant is very often made of material like polymer. The inter-metal dielectric layer with a low dielectric constant is easily damaged by oxygen plasma while stripping the photo-resist layer. The resultant dual damascene
114
(shown in
FIG. 1D
) is thus poisoned to cause an out-gassing phenomenon when the opening
114
is filled with the conductive layer
116
. The out-gassing phenomenon frequently results in a bad contact between the conductive layer
116
and the underlying metal wire
102
, even causes an open circuit therebetween.
SUMMARY OF THE INVENTION
The invention provides a method for fabricating a metal interconnect structure. An insulating layer with a low dielectric constant is used to reduce a RC delay time. By the invention, the problems of the insulating layer damaged by the oxygen plasma and the poisoned dual damascene opening can be resolved.
In one embodiment of the invention, a substrate with a first conductive layer is provided. A first insulating layer and a second insulating layer with a low dielectric constant are sequentially formed on the substrate. The second insulating layer is patterned to form a first opening positioned above the first conductive layer to expose a part of the first insulating layer. A third insulating layer is formed in the first opening and on the second insulating layer. The third insulating layer within the first opening and the first insulating layer underlying the first opening are patterned to form a second opening which exposes a part of the first conductive layer. The material of the third insulating layer is compact. The third insulating layer is formed with a high density and sufficiently compact to prevent the second insulating layer from being damaged while removing a photo-resist layer formed for patterning a second opening. The second and the first openings are then filled with a second conductive layer.


REFERENCES:
patent: 5578523 (1996-11-01), Fiordalice et al.
patent: 5759906 (1998-06-01), Lou
patent: 5913140 (1999-06-01), Roche et al.
patent: 5916823 (1999-06-01), Lou et al.
patent: 6037664 (2000-03-01), Zhao et al.
patent: 6114233 (2000-09-01), Yeh

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