Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-11-30
2001-11-06
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S290000, C257S317000, C257S431000, C365S185320
Reexamination Certificate
active
06313502
ABSTRACT:
BACKGROUND OF THE INVENTION
The invention relates to a semiconductor device comprising a semiconductor body with a surface region of a first conductivity type adjoining a surface, which semiconductor body is provided at the surface with a non-volatile memory which is erasable by means of UV irradiation and which comprises a number of memory cells, each in the form of a field effect transistor with source and drain zones of the opposed, i.e. the second conductivity type, a floating gate situated above the channel between the source and drain zones, and a control gate situated above the floating gate.
Non-volatile memories are generally known. Conventional embodiments of the transistor have a floating gate of the n-channel type with source and drain zones of the n-type and a surface region of the p-type. An n-channel embodiment will be described below. In principle however, embodiments of the opposed conductivity type are also possible. Information is written in the form of electric charge on the floating gate, thus defining the threshold voltage of the transistor. Depending on the stored information, the threshold voltage in a memory cell has a (comparatively) high or a (comparatively) low value. A voltage lying between these two values is applied to the control gate for the purpose of reading, and it is ascertained whether the transistor is, or is not, conducting.
It is possible, for the purpose of writing, to provide a negative charge on the floating gate by means of injection of hot electrons from the channel of a selected cell, thereby causing the threshold voltage of the n-channel transistor to increase to a high value. The cell can be erased through irradiation with electromagnetic radiation in the UV region, hereinafter referred to as UV radiation for short. The UV radiation forms electrons in the floating gate of sufficient energy for flowing across the potential barrier of the gate oxide between the channel and the floating gate towards the semiconductor body. When a sufficient number of electrons have disappeared from the floating gate, a state with a low threshold voltage has been obtained again.
It was found in practice that the threshold voltage often does not return to its original value, for example 1.1 V, during UV erasure, but to a much higher value, for example 2 V. This high threshold voltage may give rise to problems in, for example, low-voltage or low-power applications. A memory cell which is programmed in the “ON” state (low threshold) must have a threshold voltage which is substantially lower than the supply voltage. It is indeed possible to generate higher voltages with an on-chip charge pump, but such a charge pump is often not attractive on account of its high dissipation.
SUMMARY OF THE INVENTION
Therefore, the invention has for its object to provide, inter alia, a non-volatile, UV-erasable memory in which a lower threshold voltage is obtained during UV-erasure. According to the invention, a semiconductor device of the kind described in the opening paragraph is for this purpose characterized in that means are present for generating a photovoltage during the erasure by means of UV irradiation, which photovoltage is supplied to the control gate. The invention is based inter alia on the recognition that in a thermodynamic equilibrium, when the Fermi levels are the same, a built-in voltage is present between the n-type floating gate and the p-type substrate. The n-type floating gate has a potential at room temperature which is approximately 1 V higher than the potential in the substrate in the case of a usual doping level. This potential difference prevents that all electrons applied to the floating gate during writing return to the substrate again during erasing. The application of a negative voltage to the control gate during erasing renders it possible to compensate for part of the built-in voltage, so that more electrons will disappear from the floating gate during erasing. The use of a photovoltage generated during the UV irradiation itself as the voltage applied to the control gate renders it unnecessary to use separate, external voltage sources.
A specific embodiment of a semiconductor device according to the invention is characterized in that said means comprise a photodiode in the form of a surface zone of the second conductivity type which is provided in the surface region and which is conductively connected to the control gate, said photodiode being accessible to said electromagnetic radiation over at least part of its surface area. The photodiode may at the same time act as a protection diode which protects the control gate against electrostatic breakdown which may result from a storage of electric charge on the gate during certain process steps such as, for example, plasma etching.
A major embodiment of a device according to the invention is characterized in that the memory cells are arranged in a system of rows and columns, the control gates of cells in a common row being connected to a common photodiode via a word line.
The word lines are connected not only to the photodiode, but also to the drains of an n-channel MOST and a p-channel MOST via an output of a decoder circuit. By means of the photovoltage generated by the photodiode, it is possible, for example in the case of an n-channel floating gate transistor whose control gate is connected to the cathode of the photodiode, to bias the pn junction between the n-type drain of the n-channel MOST and the p-type surface region in the forward direction, which can cause a reduction in the photovoltage. This reduction can be easily restricted to an acceptable level, for example in that the surface area of the drain is made as small as possible. A greater leakage current is caused by the connection between the word line and the p-type drain of the p-channel MOST of the decoder circuit. The p-channel MOST is formed in an n-well which is provided in the p-type surface region and which forms a photosensitive pn junction having a comparatively large surface area with the p-type surface region. The drain together with the n-well and the p-type surface region forms a vertical pnp transistor whose emitter is formed by the p-type surface region, the base is formed by the n-well, and the collector is formed by the p-type drain, the base current being supplied by the photocurrent across the pn junction of well and surface region. A preferred embodiment of a semiconductor device according to the invention is characterized in that the memory is provided with a decoder circuit comprising a field effect transistor with a surface region, hereinafter referred to as well, of the second conductivity type in which a source and a drain of the first conductivity type of the transistor are provided, while the word line is connected to the drain, and means are present for shielding the well at least locally against incident UV radiation. Shielding the well at least locally reduces the photocurrent in the well, and thus also the current level of said parasitic transistor. A preferred embodiment of a semiconductor device according to the invention is characterized in that further means are present for suppressing parasitic transistor action between the drain, the well, and the surface region of the first conductivity type. A first embodiment is characterized in that said further means comprise a heavily doped surface zone of the second conductivity type which is provided next to the well in the surface region of the first conductivity type and which is conductively connected to this surface region. The well, the surface region of the first conductivity type, and the heavily doped surface zone of the second conductivity type form the emitter, the base and the collector, respectively, of a lateral bipolar transistor with a short-circuited base-collector junction. Part of the generated photocurrent which is collected by the well is drained off to the substrate by this transistor, so that also the current in said vertical parasitic transistor is reduced. A second embodiment is characterized in that said further means compr
Biren Steven R.
Eckert II George C.
Lee Eddie
U.S. Philips Corporation
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