Selective CVD TiSi2 deposition with TiSi2 liner

Details Selective CVD TiSi2 deposition with TiSi2 liner Selective CVD TiSi2 deposition with TiSi2 liner

2000-06-19

2001-11-13

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S412000, C257S382000

Reexamination Certificate

active

06316811

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of improving the quality and uniformity of a selective TiSi
2
deposition in the fabrication of integrated circuits.
(2) Description of the Prior Art
It is well known that it is very difficult to form a high quality uniform TiSi
2
film on narrow polysilicon lines, especially in deep sub-micron devices. One of the methods that has been used to overcome this technology barrier is to selectively deposit TiSi
2
onto the polysilicon and active silicon areas. The advantage of this approach is that there is no consumption of silicon at the source/drain regions.
Although selective CVD TiSi
2
is a promising technique, it has been found that the localized deposition rate is a strong function of the quality of the polysilicon and silicon surfaces—cleanliness, damage, etc.
FIG. 1
illustrates a typical example of the effects that polysilicon etch damage on the sidewalls of the polysilicon line can have on the CVD TiSi
2
deposition. A polysilicon line
16
is shown on the surface of a semiconductor substrate
10
. TiSi
2
21
has been selectively deposited on the top surface of the polysilicon line. It can be seen that excess TiSi
2
23
deposited at the edges of the polysilicon line due to polysilicon sidewall roughness. In practice, an insulating spacer will be formed on the sidewalls of the polysilicon line. However, the top portion of the spacers is etched away by wet chemicals leaving the top corners of the polysilicon line exposed. The roughness of the top corners of the lines causes the excess TiSi
2
deposition at the edges of the polysilicon lines.
U.S. Pat. No. 5,023,201 to Stanasolovich et al teaches forming a TiSi
2
layer on the substrate and then selectively depositing tungsten overlying the TiSi
2
and annealing to transform the TiSi
2
to the C54 phase. The process of Stanasolovich et al is not adequate for deep sub-micron polysilicon lines. U.S. Pat. No. 5,672,544 to Pan, U.S. Pat. No. 5,668,024 to Tsai et al, U.S. Pat. No. 5,593,924 to Apte et al, and U.S. Pat. No. 4,933,994 to Orban show other salicide processes using TiSi
2
.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide an effective and very manufacturable method of fabricating a silicided polysilicon gate and source/drain regions in the fabrication of an integrated circuit.
A further object of the invention is to provide a method of improving the uniformity and quality of the silicide film in the fabrication of a silicided polysilicon gate.
Yet another object is to provide a method of siliciding a polysilicon gate and source and drain regions which will eliminate the effect of surface cleanliness, damage, or residues on the deposition rate of the silicide.
Yet another object is to provide a method of siliciding a polysilicon gate and source/drain regions wherein the surface quality of the underlying polysilicon or silicon is not a factor in the quality of the silicide.
A still further object of the present invention is to provide an effective and very manufacturable method of fabricating a silicided polysilicon gate and source/drain regions for deep sub-micron devices in the fabrication of an integrated circuit.
In accordance with the objects of this invention a method for improving the quality and uniformity of a silicide film in the fabrication of a silicided polysilicon gate and source/drain regions in an integrated circuit device is achieved. A polysilicon gate electrode is provided on the surface of a semiconductor substrate. Source and drain regions are formed within the semiconductor substrate adjacent to the gate electrode. A layer of titanium is deposited over the surfaces of the substrate. The substrate is annealed whereby the titanium layer is transformed into a first titanium silicide layer except where the titanium layer overlies the spacers. The titanium layer overlying the spacers is stripped to leave the first titanium silicide layer only on the top surface of the gate electrode and on the top surface of the semiconductor substrate overlying the source and drain regions. A second titanium silicide layer is selectively deposited on the first titanium silicide layer to complete formation of the silicided gate electrode and source and drain regions in the fabrication of an integrated circuit device. The first titanium silicide layer reduces or eliminates the effect of the polysilicon and silicon surface effects allowing for a higher quality and more uniform second titanium silicide layer.
Also in accordance with the objects of this invention, an integrated circuit device having a silicided polysilicon gate with improved silicide quality and uniformity is achieved. The integrated circuit device of the present invention comprises a polysilicon gate electrode on the surface of a semiconductor substrate, source and drain regions within the semiconductor substrate adjacent to the polysilicon gate electrode, and dielectric spacers on the sidewalls of the gate electrode. A lining silicide layer overlies the top surface of the gate electrode and the surface of the semiconductor substrate overlying the source and drain regions. A second silicide layer overlies the lining silicide layer. A patterned conducting layer contacts the silicided gate electrode and source and drain regions through openings in an overlying insulating layer to complete the integrated circuit device.


REFERENCES:
patent: 4933994 (1990-06-01), Orban
patent: 5023201 (1991-06-01), Stanasolovich et al.
patent: 5593924 (1997-01-01), Apte et al.
patent: 5668024 (1997-09-01), Tsai et al.
patent: 5672544 (1997-09-01), Pan
patent: 5744395 (1998-04-01), Shue et al.
patent: 5858846 (1999-01-01), Tsai et al.
patent: 6156649 (2000-12-01), Hause et al.
patent: 0724287A2 (1996-07-01), None
patent: 409283464A (1997-10-01), None

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