Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2000-06-01
2001-11-20
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S210130, C365S230060, C365S230080
Reexamination Certificate
active
06320800
ABSTRACT:
RELATED APPLICATION
This application claims the benefit of priority under 35 U.S.C. §119 of Japanese Patent Applications Nos. H11-156255, filed on Jun. 3, 1999, and 2000-65398 filed on Mar. 9, 2000, the entire contents of which are incorporated by reference herein.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to an electrically rewritable semiconductor memory, such as an EEPROM. More specifically, the invention relates to a semiconductor memory having a redundant circuit for replacing a defective memory cell.
2. Description of the Related Background Art
In typical large scale semiconductor memories, a redundant circuit system for relieving a device having a certain range of defective memory cells is adopted in order to improve producing yields. The redundant circuit systems include three types, i.e., a column redundant circuit for replacing a defective bit line with a spare bit line, a row redundant circuit for replacing a defective word line with a spare word line, and a combination thereof.
A memory of a redundant circuit system has a defective address storing circuit, such as a fuse circuit, for nonvolatilisably storing a defective address. Then, the coincidence of an input address with a defective address is detected to output an detection output. In response to the coincidence detection output, the memory cell of the defective address is replaced with a memory cell of a redundant circuit.
However, in conventional EEPROMs, the relief efficiency using the redundant circuit is not high Because it is not possible to cope with a plurality of defective columns or rows even if redundant circuits corresponding to one column or one row are arranged at the end portion of a memory cell array. In addition, even if redundant circuits corresponding to one column or one row are arranged at the end portion of the memory cell, there is a strong possibility that the redundant circuits themselves at the end portion of the cell array will be defective. This also lowers the relief efficiency.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a semiconductor memory capable of effectively relieving a plurality of defective columns and a defect in a boundary region in column directions.
It is another object of the present invention to provide a semiconductor memory of the RWW specification capable of efficiently columns in each bank.
It is a further object of the present invention to provide a semiconductor memory capable of effectively relieving a defective row by preventing any useless pass current paths from being produced in a data erase operation.
It is a still further object of the present invention to provide a semiconductor memory having a defective address storing circuit capable of shortening time in a defect inspection process.
The present invention is effective in the application to EEPROMs as well as other semiconductor memories such as DRAMs.
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a semiconductor memory comprises:
a memory cell array having electrically rewritable memory cells; a plurality of redundant column cell arrays for relieving a defective memory cell in the memory cell array;
a decoding circuit for selecting a memory cell of the memory cell array;
a plurality of sense amplifier circuits for detecting read data of the memory cell array and for latching write data;
data input/output buffers provided between each of the sense amplifier circuits and a corresponding one of data input/output terminals;
a defective address storing circuit for storing a defective address of the memory cell array, an input/output terminal to and from which data corresponding to the defective address are inputted and outputted, and a set number for identifying one of the plurality of redundant column cell arrays, which is to be substituted so as to correspond to the input/output terminal;
a plurality of redundant sense amplifier circuits for detecting read data of the plurality of redundant column cell arrays and for latching write data;
an address comparator circuit for outputting a coincidence detection signal when an input address is coincident with the defective address held in the defective address storing circuit; and
a switching circuit which is controlled by the coincidence detection signal for selectively connecting one of the sense amplifier corresponding to the defective address in the plurality of sense amplifier circuits or one of the redundant sense amplifier circuits identified by the set number in the plurality of redundant sense amplifier circuit, to the data input/output buffer.
According to another aspect of the present invention, a semiconductor memory comprises:
a memory cell array having electrically rewritable memory cells, the memory cell array being divided into a plurality of banks which are able to be accessed independently of each other;
at least one redundant column cell array provided in each of the banks for relieving a defective memory cell of the memory cell array;
a decoding circuit provided in each of the banks;
a first address bus line for data reading, which is provided commonly for each of the banks;
a second address bus line for data writing or erasing, which is provided commonly for each of the banks;
a first data bus line for data reading, which is provided commonly for each of the banks;
a second data bus line for data writing or erasing, which is provided commonly for each of the banks;
a plurality of first sense amplifier circuits, connected to the first data bus line, for detecting and amplifying read data of the memory cell array in parallel;
a plurality of second sense amplifier circuits, connected to the second data bus line, for detecting and amplifying verify read data of the memory cell array in parallel;
a busy signal circuit, provided in each of the banks, for outputting a busy signal indicating whether an assigned bank is selected as a data write or erase mode or a read mode, the busy signal being used for controlling the selective connection of the first and second address bus lines and for controlling the selective connection of the first and second data bus lines;
a defective address storing circuit for storing an input/output terminal, to and from which a defective address of the memory cell array and data corresponding to the defective address are inputted and outputted;
a first redundant sense amplifier circuit which is provided so as to correspond to the redundant column cell array and which is connected to the first data bus line for detecting and amplifying read data of the redundant column cell array;
a second redundant sense amplifier circuit which is provided so as to correspond to the redundant column cell array and which is connected to the second data bus line for detecting and amplifying verify read data of the redundant column cell array;
a first address comparator circuit for detecting the incidence of an address, which is supplied to the first address bus line in a data read operation, with the defective address held in the defective address storing circuit;
a second address comparator circuit for detecting the coincidence of an address, which is supplied to the second address bus line in a data write or erase operation, with the defective address held in the defective address storing circuit;
a first switching circuit for replacing a part of the output of the plurality of first sense amplifier circuits with the output of the first redundant sense amplifier circuit, on the basis of a coincidence detection output of the first address comparator circuit; and
a second switching circuit for replacing a part of the output of the plurality of second sense amplifier circuits with the output of the second redundant sense amplifier circuit, on the basis of a coincidence detection output of the second address comparator circuit.
According to a further aspect of the present invention, a semiconductor memory comprises:
a memory cell array having electrically rewritable memory cells, t
Honda Yasuhiko
Kato Hideo
Kuriyama Masao
Saito Hidetoshi
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
Le Thong
Nelms David
LandOfFree
Semiconductor memory and nonvolatile semiconductor memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory and nonvolatile semiconductor memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory and nonvolatile semiconductor memory... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2579132