Semiconductor memory with a decoder circuit having a...

Details Semiconductor memory with a decoder circuit having a... Semiconductor memory with a decoder circuit having a...

2000-05-24

2001-11-20

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S185200, C365S189090, C365S201000, C365S210130

Reexamination Certificate

active

06320799

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory and in more specific terms, it relates to a semiconductor memory provided with a decoder circuit having a redundancy relief function.
2. Description of the Related Art
A semiconductor memory such as a DRAM is normally provided with a column redundancy circuit that employs an ATD (address transition detector) or a shift-type redundancy circuit, to achieve an improvement in the yield. Of the two types of redundancy circuits, the shift-type redundancy circuit can be achieved through a simpler circuit structure compared to a column redundancy circuit employing an ATD and does not require as much time for the column line to enter an active state.
A semiconductor memory provided with a shift-type redundancy circuit is explained below in reference to FIG.
6
. The semiconductor memory in the prior art, which constitutes a DRAM, includes a column decoder circuit CD
1
, a memory cell sub-array MCA and a sense amplifier sub-array SAA The shift-type redundancy circuit constitutes part of the column decoder circuit CD
1
.
The memory cell sub-array MCA is provided with a plurality of memory cells MCij (i=0, 1, . . . , j=0, 1, . . . , 255). The individual memory cells MCij are connected to a plurality of word lines WL(
0
), WL (
1
), . . . , WL(i), . . . , and the plurality of complementary bit line pairs BL(
0
)/BLb(
0
), BL(
1
)/BLb(
1
), . . . , BL(j)/BLb(j), . . . , BL(
255
)/BLb(
255
), and are arranged at individual points of intersection in a matrix.
Each memory cell MCij constitutes a so-called 1-transistor memory cell comprising an N-type transistor (not shown) and a capacitor (not shown) with the gate, the drain and the source of the N-type transistor respectively connected with the word line WL(i), the bit line BL(j) and one end of the capacitor. At the other end of the capacitor constituting each memory cell MCij, a voltage at a level that is halfway between the source voltage Vcc of the DRAM and the substrate voltage Vss is applied.
The sense amplifier sub-array SAA located adjacent to the memory cell sub-array MCA is provided with a plurality of sense amplifiers SA(
0
), SA(
1
), . . . , SA(
255
) and a plurality of data transfer circuits DT(
0
), DT(
1
), . . . , DT(
255
). The bitline pair BL(j)/BLb(j) is connected to a data transfer circuit DT(k) via a sense amplifier SA(k) (k=0, 1, . . . , 255), and the data transfer circuit DT(k) is further connected with a data bus pair LDB/LDBb and a column line CL(k).
The operation achieved in the DRAM constituting the semiconductor memory in the prior art illustrated in
FIG. 6
is now explained. When the word line WL(i) is selected, data that are stored as an electrical charge at the memory cell MCij connected to the word line WL(i) are output to the bit line BL(j), thereby generating a potential difference at the bit line pair BL(j)/BLb(j). The sense amplifier SA(k) detects the potential difference at the bit line pair BL(j)/BLb(j) and amplifies the potential difference.
If the column line CL(k) is selected by the column decoder circuit CD
1
and is set to the source voltage Vcc, the data transfer circuit DT(k) connected with the column line CL(k) enters an ON state, and the bit line pair BL(j)/BLb(j) and the data bus pair LDB/LDBb become electrically continuous. As a result, the data amplified by the sense amplifier SA(k) are transferred to the data bus pair LDB/LDBb. Thus, a data read operation from the MCij is achieved. It is to be noted that the DRAM in the prior art illustrated in
FIG. 6
is provided with an auxiliary column line CLr.
Next, the structure of the column decoder circuit CD
1
is explained in reference to FIG.
7
. The column decoder circuit CD
1
is provided with fuse blocks FB(
0
), . . . , FB(k), FB(k+1), . . . , FB(
255
), decoders D(
0
), . . . , D(k), D(k+1), . . . , D(
255
), redundancy control circuits RL(
0
), . . . , RL(k), RL(k+1), . . . , RL(
255
) and RLr, column line drivers DV
1
(
0
), . . . , DV
1
(k), DV
1
(k+
1
), . . . , DV
1
(
255
) and DV
1
r, a fuse driver FDV and a pre-charge circuit PC.
The fuse block FB(k) is provided with two fuses FU
0
(k) and FU
1
(k) that are independent of each other. The fuse FU
0
(k) and the fuse FU
1
(k) are connected to the redundancy control circuit RL(k) via a fuse node F
0
(k+1) and a fuse node F
1
(k+1) respectively. In addition, the fuse FU
0
(k) and the fuse FU
1
(k) are respectively connected to a fuse FU
0
(k+1) and a fuse FU
1
(k+1) in the adjacent fuse block FB(k+1) via the fuse node F
0
(k+1) and the fuse node F
1
(k+1). As a result, the fuses FU
0
(
0
)~FU
0
(
255
) and FU
1
(
0
)~FU
1
(
255
) in the fuse blocks FB(
0
)~FB(
255
) are connected in series along the direction in which the word lines WL extend over the entire column decoder circuit CD
1
.
The decoder D(k) is constituted as a 4-input NAND gate to which input column address signals PY
76
, PY
53
, PY
21
and PY
0
are input. The output terminal of the decoder D(k) is connected to the redundancy control circuit RL(k) and also to the adjacent redundancy control circuit RL(k+1), so that an output signal YD(k+1) output by the decoder D(k) is input to the redundancy control circuits RL(k) and RL(k+1). The input column address signals PY
76
, PY
53
, PY
21
and PY
0
are pre-decoded signals. The input column address signal PY
76
is a signal achieved by pre-decoding addresses
6
and
7
and has a 4-bit width. The input column address signal PY
53
is a signal achieved by pre-decoding addresses
3
~
5
and has an 8-bit width. The input column address signal PY
21
is a signal achieved by pre-decoding addresses
1
and
2
and has a 4-bit width. The input column address signal PY
0
is a signal achieved by pre-decoding address
0
and has a 2-bit width. For instance, the lowest order bit among the four bits of the input column address signal PY
76
is input to the decoders D(
0
), D(
4
), D(
8
), . . . , D(
252
), the second bit maybe input to the decoders D(
1
), D(
5
), D(
9
), . . . , D(
253
), the third bit is input to the decoders D(
2
), D(
6
), D(
10
), . . . , D(
254
) and the highest-order bit is input to the decoders D(
3
), D(
7
), D(
11
), . . . , D(
255
). Likewise, the individual bits in the input column address signals PY
53
, PY
21
and PY
0
are sequentially input to the decoders D(
0
)~D(
255
). In this structure, a single decoder D(k) corresponding to the column address is selected. It is to be noted that in the following explanation, a pre-decoded signal is referred to as an input column address signal.
The redundancy control circuit RL(k−1) (not shown), the redundancy control circuit RL(k) and the redundancy control circuit RL(k+1) are arranged over multiple stages along the direction in which the word lines WL extend, with redundancy selection signals RE(k) and REb(k) output by the redundancy control circuit RL(k−1) input to the redundancy control circuit RL(k) and redundancy selection signals RE(k+1) and REb(k+1) output by the redundancy control circuit RL(k) input to the redundancy control circuit RL(k+1). The redundancy control circuit RL(k) is connected with the column line driver DV
1
(k) which drives the column line CL(k) via a node DEC(k). Redundancy selection signals RE(
0
) and REb(
0
) input to the redundancy control circuit RL(
0
) are respectively set to the substrate voltage Vss and the source voltage Vcc.
Redundancy selection signals REr and RErb output by the redundancy control circuit RL(
255
) and an output signal YDr from the decoder D(
255
) are input to the auxiliary redundancy control circuit RLr. The redundancy control circuit RLr is connected to the column line driver DV
1
r that drives the auxiliary column line CLr via a node DECr.
The pre-charge circuit PC is connected to the fuse block FB(
255
) which corresponds to the column line CL(
255
) via fuse nodes F
0
c and F
1
c. The pre-charge circuit PC charges of the fuses FU

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