Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver
Reexamination Certificate
2000-08-21
2001-12-04
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Current driver
C327S398000, C326S087000
Reexamination Certificate
active
06326822
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a system in which a data bus is used, and more particularly, to an apparatus and method for driving a bus with low power consumption.
2. Description of the Related Art
As portable systems such as palm top computers, smart phones, and personal digital assistants are widely used, the demand for integrated circuits with low power consumption is rapidly increasing. This is because it is important to secure a certain level of operation time using restricted power of batteries in portable systems.
At this time, reducing power consumption by a data bus is important to developing the integrated circuits in which low power consumption is required. This is because power consumed in the bus accounts for a considerable amount of power consumed in the entire integrated circuit. In general, a bus driving apparatus generates a bus driving voltage, corresponding to the binary logic level of input data, and transmits the generated bus driving voltage to the bus receiving apparatus through the data bus. At this time, the bus receiving apparatus restores the bus driving voltage received through the data bus to original input data. At this time, the data bus consumes power since a parasitic capacitance of the generally long data bus Cw is charged or discharged whenever the logic level, of the bus driving voltage changes.
In the conventional bus driving apparatus, the width of the change in the level of the bus driving voltage (or the swing width of the bus driving voltage) transmitted to the bus receiving apparatus through the data bus is very large. Therefore, since a large amount of charge is charged or discharged in the parasitic capacitor Cw, power consumption by the data bus becomes larger.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide an apparatus and method for driving a bus with low power consumption, capable of reducing power consumption by reducing the width of the change in a bus driving voltage transmitted through the data bus.
Accordingly, in accordance with the invention, there is provided an apparatus for driving a data bus, in which a first or second bus driving voltage, corresponding to input data, is transmitted to a bus receiving apparatus through a data bus instead of the input data. The apparatus includes a first voltage transmitter for transmitting the first bus driving voltage to the data bus in response to a control signal, the first bus driving voltage corresponding to input data having a high level. A second voltage transmitter transmits the second bus driving voltage to the data bus in response to the control signal, the second bus driving voltage having a level that is lower than the level of the first bus driving voltage by a predetermined difference level and corresponding to a low level of the input data. A control signal generator outputs the control signal in response to the input data. A voltage reducer reduces the first bus driving voltage transmitted to the data bus by a voltage having a level higher than or equal to the predetermined difference level in response to the input data and the control signal when the input data transitions from the high level to the low level.
In one embodiment, the apparatus for driving the bus is included in an integrated circuit together with the data bus.
The first voltage transmitter can include a first PMOS transistor having a gate connected to the control signal and a source and a drain connected to a supply voltage and the data bus, respectively.
The second voltage transmitter can include a first NMOS transistor having a gate connected to the control signal and a drain and a source connected to a supply voltage and the data bus, respectively. The predetermined difference level can correspond to the level of the gate-to-source threshold voltage of the first NMOS transistor. The second voltage transmitter can include second through Mth NMOS transistors, where M is a positive integer larger than or equal to two. The drain and gate of each of these NMOS transistors can be electrically connected to each other. The second NMOS transistor can include a drain connected to the source of the first NMOS transistor. An Xth (3≦X≦M−1) NMOS transistor can include a drain and a source connected to the source of an (X−1)th NMOS transistor and the drain of an (X+1)th NMOS transistor, respectively. The Mth NMOS transistor can include a drain and a source connected to the source of the (M−1)th NMOS transistor and the data bus, respectively. The voltage having the predetermined difference level can be obtained by adding the gate-to-source threshold voltages of the first through Mth NMOS transistors to each other.
In one embodiment, the voltage reducer comprises a delay for delaying the control signal for a predetermined time required for reducing the first bus driving voltage transmitted to the data bus by the voltage having the level higher than or equal to the predetermined difference level and outputting the delayed control signal. The voltage reducer also includes OR operation means for performing an OR operation on the delayed control signal obtained by the delay and the input data and outputting the OR operation result. The voltage reducer also includes a second PMOS transistor having a gate connected to the OR operation result and a source and a drain connected to the data bus and a reference voltage, respectively.
In another aspect of the invention, there is provided an apparatus for driving a data bus, in which a first or second bus driving voltage, corresponding to input data, is transmitted to a bus receiving apparatus through a data bus. The apparatus includes a first voltage transmitter for transmitting the first bus driving voltage to the data bus in response to a control signal, the first bus driving voltage corresponding to input data having a low level. A second voltage transmitter transmits the second bus driving voltage to the data bus in response to the control signal, the second bus driving voltage having a level that is higher than the level of the first bus driving voltage by a predetermined difference level and corresponding to a high level of the input data. A control signal generator outputs the control signal in response to the input data. A voltage adder adds a voltage having a level higher than or equal to the predetermined difference level to the first bus driving voltage transmitted to the data bus in response to the input data and the control signal when the input data transitions from the low level to the high level.
In one embodiment of this aspect of the invention, the apparatus for driving the bus is included in an integrated circuit together with the data bus.
The first voltage transmitter can include a first NMOS transistor having a gate connected to the control signal and a drain and a source connected to the data bus and a reference voltage, respectively.
The second voltage transmitter can include a first PMOS transistor having a gate connected to the control signal and a source and a drain connected to the data bus and a reference voltage, respectively. The predetermined difference level can correspond to the level of the source-to-gate threshold voltage of the first PMOS transistor. The second voltage transmitter can include second through Mth PMOS transistors, where M is a positive integer larger than or equal to two. The drain and gate of each of these PMOS transistors can be electrically connected to each other. The second PMOS transistor can include a drain connected to the source of the first PMOS transistor. An Xth (3≦X≦M−1) PMOS transistor can include a drain and a source connected to the source of an (X−1)th PMOS transistor and the drain of an (X+1)th PMOS transistor, respectively. The Mth PMOS transistor can include a drain and a source connected, to the source of the (M−1)th PMOS transistor and the data bus, respectively. The voltage having the predetermined difference level can be obtained by adding the source-to-gate t
Mills & Onello LLP
Nguyen Hai L.
Samsung Electronics Co,. Ltd.
Tran Toan
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