Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2000-11-13
2001-11-20
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S063000
Reexamination Certificate
active
06320815
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor memory systems and in particular to a memory system of the type having a single controller and multiple memory devices communicating with the controller by way of a flexible bus structure that permits the system to accommodate a wide number and variety of memory devices.
2. Description of Related Art
Semiconductor memories having increased storage capacity have been developed. A typical memory system may include a single memory controller implemented on a single integrated circuit together with one or more memory devices, each of which is implemented on a single integrated circuit, having an array of memory cells. The memory controller and memory devices are typically connected by way of a bus so that the controller can issue memory read, program and erase commands to a selected one of the memory devices.
In order to increase the storage capacity of a memory system, it is possible that a large number of separate integrated circuit memory devices may be utilized in the system. However, a typical memory system bus includes an address bus, a data bus and various control pins such as Chip Enable (CE), Output Enable (OE), Write Enable (WE) and the like. This type of configuration increases the pin count of the integrated circuit memory devices and power requirements. Further, the use of separate control pins for each integrated circuit memory device increased the complexity of the system bussing.
A memory system-of the type having a memory controller and a plurality of separate memory devices which share the same flexible bus structure would be highly desirous. Ideally, such a system would allow the same architecture for different storage capacities and would permit both forward and backward flexibility so that so that several generations of the separate memory devices can operate at the same time with the same controller. Further, the system would allow memory devices to be used having a reduced pin count so an to reduce complexity, manufacturing costs and increase relaility.
The present invention provides the above-noted advantages as will be recognized by those skilled in the art upon a reading of the following Detailed Description of the Preferred Embodiment together with the drawings.
FIG. 1
depicts a simplified conventional memory system which includes a host device
20
, an address decoder
22
and memory devices
24
A and
24
B. The host device
22
may be a microprocessor and the memory devices
24
A and
24
B may be separate memory integrated circuits. An address bus
26
is used to provide addresses to an address decoder
22
and to the memory devices
24
A and
24
B. The address decoder
22
has two outputs connected to enable inputs of the memory devices
24
A and
24
B. Typically, the most significant bit(s) of the address are provided on the bus
26
to the decoder
22
, with the remaining address bits being provided to each of the memory devices.
When memory is to be accessed, the processor
20
causes the address decoder
22
to decode the most significant bit(s) of the memory address placed on an address bus
26
. The decoder
22
will select one of the two memory devices
24
A and
24
B by generating either signal Sel
0
or Sel
1
. The selected memory device will respond to the address presented to it on the address bus and the deselected memory device, which is disabled, will not respond. Although not shown, a data bus is used to transfer data between the memory devices and the processor
20
, with only the selected device outputting data to the data bus during memory read operations.
The approach depicted in
FIG. 1
is sometimes referred to as radial device selection where each memory device has a separate select input. This approach works well when relatively few memory devices are employed and where access speed, particularly random access speed, is important. However, if a large number of memory devices are used so that large amounts of data can be stored, the requirement of separate select lines for each memory device results in large memory boards and a relatively large pin count for the control logic circuitry. Thus, unless access speed is critical and a large number of memory devices are used, the radial device selection approach of
FIG. 1
is not ideal.
FIG. 2
shows an alternative prior art device selection technique, sometimes referred to as serial selection. Again, a host device
28
is used which is connected to several memory devices
30
A,
30
B and
30
C by way of a system bus
32
. The memory devices
30
A,
30
B and
30
C are usually implemented as separate integrated circuits. The system bus
32
includes memory address and memory data and various control signals so that each of the memory devices
30
A,
30
B
30
C receives the same addresses, data and other signals. Each memory device is preassigned a unique address so that only one device will be accessed by the host device
28
during a memory operation. Typically, the memory devices
30
A,
30
D and
30
C are assigned addressee by way of jumper or switch settings represented by elements
34
A,
34
B and
34
C.
The
FIG. 2
approach requires that dedicated pins be provided on each of the integrated circuit memory devices
30
A,
30
B and
30
C to receive the jumper wires or switches for assigning the addresses. These pins increase the pin count for the integrated circuits thereby increasing the cost of the packaging for the devices and increasing the likelihood that there will be mechanical problems and manufacturing errors through soldering and the like. These extra pins are also subject to defects and increase the possibility of damage to the integrated circuits as a result of electrostatic discharge.
SUMMARY OF THE INVENTION
A memory system comprising a memory controller and a plurality of memory devices coupled to a common system bus is disclosed. The memory controller is configured to issue device select instructions, memory program instructions and memory read instructions over the system bus. The device select instructions include a device select command and a device select address.
The memory devices are each switchable between a device-enabled state where memory read operations can be carried out on the memory device and a device-disabled state where memory read operations cannot be carried out. Each of the memory devices further includes an array of memory cells and a memory operation manager coupled to the system bus and to the array. The memory operation manager, which is configured to carry out the memory read and memory program operations, includes an address comparator configured to compare a local address for the memory device to an address received from the memory controller on the system bus and a command decoder configured to detect commands received from the memory controller on the system bus. The memory operation manager is further configured to switch the memory device to the device-enabled state when command decoder and address comparator indicate that one of the device select commands has been detected on the system bus together with an address on the system bus which matches the local address.
Preferably, the memory controller is configured to issue a device deselect command on the system bus together with a device deselect address on the system bus. In that event, the memory operation manager is further configured to switch the memory device to the device-disabled state when the command decoder and address comparator indicate that one of the device deselect command has been detected on the system bus together with the device deselect address on the system bus which matches the local address.
REFERENCES:
patent: 5201056 (1993-04-01), Daniel et al.
patent: 5305442 (1994-04-01), Pederson et al.
patent: 5414827 (1995-05-01), Lin
patent: 5517625 (1996-05-01), Takahashi
patent: 5870579 (1999-02-01), Tan
patent: 6073204 (2000-06-01), Lakhani et al.
patent: 6078985 (2000-06-01), Lakhani et al.
patent: 6247101 (2001-06-01), Setties et al.
Chevallier Christophe J.
Lakhani Vinod C.
Norman Robert D.
Dinh Son T.
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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