Active solid-state devices (e.g. – transistors – solid-state diode – Encapsulated
Reexamination Certificate
1999-08-25
2001-12-18
Clark, Jhihan B. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Encapsulated
C257S693000, C257S783000, C257S792000
Reexamination Certificate
active
06331737
ABSTRACT:
The present invention is related in general to the field of semiconductor devices and processes, and more specifically to encapsulation methods for integrated circuit chips resulting in thin and substantially flat packages having substantially the same outline as the circuit chip.
BACKGROUND OF THE INVENTION
During the last few years, a major trend in the semiconductor industry has been the efforts to shrink semiconductor packages so that the package outline consumes less area and less height when it is mounted onto customer circuit boards, and to reach these goals with minimum cost (both material and manufacturing cost). One of the most successful approaches has been the development of so-called “chip-scale packages”. These packages have an outline adding less than 20% to the chip area. A chip-scale package which has only the outline of the chip itself, is often referred to as “chip-size package”. While a number of designs have been successfully demonstrated to achieve substantially flat packages having substantially the same outline as the circuit chip, the reduction in device thickness has been quite limited and essentially elusive.
One of the earliest successful approaches to chip-scale packaging includes the use of sheet-like polymer interposers between and/or around elements of the semiconductor packages in order to reduce and/or redistribute the strain and stress on the connections between the semiconductor chip and the supporting circuitized substrate during operation of the chip. A description can be found for instance in U.S. Pat. No. 5,148,266, Sep. 15, 1992 (Khandros et al.) entitled “Semiconductor Chip Assemblies having Interposer and Flexible Lead”. It introduces a spacer layer (made of compliant or elastomeric material) between a top surface of a sheet-like substance and a contact bearing surface of a semiconductor chip, wherein the substrate has conductive leads thereon, the leads being electrically connected to terminals on a first end and connected to respective chip contacts to a second end.
In U.S. Pat. No. 5,776,796, Jul. 7, 1998 (Distefano et al.) entitled “Method of Encapsulating a Semiconductor Package”, the encapsulation method introduces curable liquids such as electronic grade silicone-based-or epoxy-based resins by using needle-like dispensers, moving around the periphery of the chip, until the desired level of encapsulant has been substantially uniformly dispensed. Dependent on the material, the encapsulant is then cured by radiant energy, thermal energy, moisture, or ultraviolet light. Typically, this encapsulation method is performed simultaneously on a plurality of chips which are sharing a common frame. Finally, a dicing saw, water jet, ultrasonic knife, rotary razor, or laser separates the encapsulated chip assembly structure from the frame so that the resultant chip package is no, or only slightly, wider than the periphery of the chip itself. With some effort, the encapsulate will not flow onto the back surface of the chip; it can thus subsequently be connected to a heat sink without an insulative material impeding the dissipation of heat from the chip.
Within the semiconductor memory product families, one of the most promising concepts for chip-scale packages is the so-called “board-on-chip” design. Recently, patent application entitled “Chip-size Integrated Circuit Package” has been filed by Texas Instruments in Singapore on Jul. 2, 1997 under Ser. No. 9702348-5, and in the USA on Dec. 19, 1997 under Ser. No. 08/994,627. An approach to reduce the package height and to reach a low device profile with the board-on-hip design has been described in the patent applications entitled “Thin Chip-size Integrated Circuit Package and Method of Fabrication” filed in Singapore on Jan. 2, 1998 under Ser. Nos. 9800005-2 and 9800006-0. These devices use wire ball bonding for assembly; because of the extreme sensitivity of the thin wires against mechanical disturbances, careful protection by reliable encapsulation is needed; liquid potting material is dispensed by needle-like syringes and later cured. If solder balls are used to assemble the devices on circuit boards, this encapsulation has to withstand the mechanical stress caused by the difference in thermal expansion coefficients of the material involved.
Since all these approaches to chip-scale package the process of encapsulating the device comprises distributing semi-viscous material from the openings of syringes onto preselected regions of the device surfaces to be covered, and then distributing the material over the whole area and into openings to be filled with the help of capillary forces, this technology obviously suffers from-several shortcomings. Foremost, the existing technology is not economical. In order to keep the number of dispensers in practical limits, only a modest number of packages can be encapsulated in one fabrication step; the process does not lend itself to mass production. Secondly, the process is hard to control uniformly, and prone to statistical variations such as uneven fillings, pronounced meniscus formation, or flaws such as voids. It has been the experience over several years of production that a high percentage of the devices exhibit cosmetic flaws. Further, the choice of materials is limited to liquid materials which typically require prolonged “curing” times for polymerization and hardening, causing high mechanical stress in the product. In addition, the liquids tend to splatter onto exposed semiconductor surfaces, thus causing particulate contamination inhibiting the application of flat heat sinks.
Understandably, efforts have been expanded to apply the conventional transfer molding technology to produce thin semiconductor products. The transfer molding technology was introduced to semiconductor devices (U.S. Pat. Nos. 3,716,764 and 4,043,027) as an encapsulation process which is both gentle and reliable, and exceedingly well applicable to mass production. Over the years, transfer molding has been applied to almost all semiconductor device types, but it has proved extraordinarily difficult to produce devices thinner than about 0.8 mm total thickness. The main difficulty has been the adhesion of the molding material to the cavity walls of the steel molds, which proved to become dominant over the adhesion of the molding material to the device parts when the molded layers shrink below about 0.2 mm thickness (dependent on the chemistry of the material). The thin molded layers also tended to break after polymerization.
A partial solution arrived with U.S. Pat. No. 5,098,626 of Mar. 24, 1992 (Pas, “Method for Packing a Measured Quantity of Thermosetting Resin and Operating a Mold for Encapsulating a Component”) and U.S. Pat. No. 5,431,854 of Jul. 11, 1995 (Pas, “Method for Pressing a Plastic, which Cures by means of a Reaction, into a Mold Cavity, a Pressing Auxiliary in Pill Form to be Used in this Method, and a Holder Composed of such Material”). The emphasis is placed on cleanliness of the molding material by prepacking and sealing it in plastic forms which are only ruptured at time of usage, and on preventing the deleterious adhesion to the mold cavity walls of the molding material by covering thin continuous plastic films over the mold walls. For this purpose, the pulling forces from vacuum “dispensed” from numerous openings pressure the flexible films against the walls, thus keeping the molding material away from the walls. However, until now the so-called “3-P” technology is intended for encapsulating only standard-size semiconductor devices and does not offer the unique processes, mold designs or molding materials needed for encapsulating devices with at least one minimized geometry.
An urgent need has therefore arisen for a coherent, low-cost method of encapsulating thin semiconductor chip-scale packages. The method should be flexible enough to be applied for different semiconductor product families and a wide spectrum of design and process variations, should eliminate all cosmetic and substantial flaws in those products, and should allow the usage of various form
Lim Tiang Hock
Tay Liang Chee
Clark Jhihan B.
Honeycutt Gary C.
Navarro Arthur I.
Telecky Fred
Texas Instruments Incorporated
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