Semiconductor device including an interface layer containing...

Details Semiconductor device including an interface layer containing... Semiconductor device including an interface layer containing...

1999-09-24

2001-12-04

Thomas, Tom (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S302000

Reexamination Certificate

active

06326658

ABSTRACT:

BACKGROUND OF THE INVENTION
The element area of a semiconductor integrated circuit is gradually reduced for each generation with an increase in the integration density and miniaturization of the semiconductor integrated circuit as is represented by a DRAM. In a DRAM in which each memory cell is formed of one transistor and one capacitor, a reduction in the element area causes a reduction in the area of the capacitor for storing information so that the information storing function may be deteriorated.
Therefore, various devices are made to securely attain a sufficiently large capacitance of the capacitor so as to prevent the information storing function from being deteriorated by the high integration density and miniaturization in the DRAM. One of the devices is to form the capacitor in the 3-dimensional form, that is, use a trench capacitor or stacked capacitor.
As the trench capacitor, a structure called a substrate plate type is mainly used for the DRAM of 64 Mbit or more. The important point in the memory cell using the substrate plate type trench capacitor is the structure of a connecting portion between the storage node electrode (the electrode buried in the trench) of the capacitor and the source/drain diffusion layer of the transistor.
As one of the structures of the connecting portions, a buried strap structure is known.
FIG. 8
is a cross sectional view showing a DRAM memory cell having the buried strap structure. In
FIG. 8
, a reference numeral
80
denotes a single crystal silicon substrate,
81
a plate electrode,
82
a capacitor insulating film,
83
a collar oxide film,
84
1
,
84
2
storage node electrodes,
85
a buried strap (polysilicon film),
86
,
87
source/drain diffusion layers,
88
a gate insulating film,
89
a gate electrode and
90
an element isolation insulating film for STI (Shallow Trench isolation).
In this type of memory cell, the electrical connection between the source/drain diffusion layer
86
and the storage node electrode
86
is attained by use of the buried trap
85
. The buried strap
85
has an advantage that it can be formed in a self-alignment manner without using the photolithography process using a mask. Further, it also has an advantage that the area is not increased by formation of the buried strap
85
.
In the above type of memory cell, the following problem on the process occurred.
In a case where an oxide film such as a natural oxide film is not formed on the interface between the buried strap
85
and the single crystal silicon substrate
80
in an area used as the source/drain diffusion layer
86
, that is, when the interface is extremely clean, the epitaxial growth occurs from the side surface of the trench towards the buried strap
85
in the post process of high temperature, for example, in the formation process of the element isolation insulating film
90
.
More specifically, as shown in
FIG. 9
, a wedge-shaped epitaxial region
91
is formed in the buried strap
85
. As a result, local mechanical stress occurs and transfer
92
occurs in the substrate. The transfer
92
causes an increase in the junction leak current, thereby deteriorating the data holding characteristic of the DRAM.
BRIEF SUMMARY OF THE INVENTION
The inventors of this application and others considered to suppress the epitaxial growth by forming an oxide film or nitride film
93
on the interface as shown in
FIG. 10
so as to solve the above problem.
Since the oxide film or nitride film
93
is an insulating film, it is necessary to precisely control the film thickness thereof to an extremely small value.
However, since the control process is difficult, the contact resistance between the buried strap
85
and the source/drain diffusion layer
86
may become large or a variation in the contact resistance between the memory cells becomes large if an oxide film or nitride film
93
is formed on the interface. This causes a variation in the data readout characteristic and gives a bad influence on the device.
An object of this invention is to provide a semiconductor device having a structure in which a polycrystalline semiconductor film is formed on a single crystal semiconductor substrate and capable of preventing occurrence of transfer during the above process and an increase in the contact resistance and a method for manufacturing the same.
A semiconductor device according to an embodiment of this invention comprises a single crystal semiconductor substrate; a polycrystalline semiconductor film formed on the single crystal semiconductor substrate; and a conductive interface layer formed between the single crystal semiconductor substrate and the polycrystalline semiconductor film and formed of a material different from constituent materials of the single crystal semiconductor substrate and the polycrystalline semiconductor film.
Further, a method for manufacturing a semiconductor device according to this invention comprises the steps of forming a conductive interface layer on the surface of a single crystal semiconductor substrate by reacting gas of a material different from a constituent material of the single crystal semiconductor substrate with the single crystal semiconductor substrate; and forming a polycrystalline semiconductor film which is formed of a material different from a constituent material of the interface layer and connected to the single crystal semiconductor substrate by the interface layer. The interface layer may be formed by use of a CVD method using a material different from the constituent material of the single crystal semiconductor substrate as a raw material.
Further, a method for manufacturing a semiconductor device according to this invention comprises the steps of repeatedly adsorbing SiCl
4
to a surface of a single-crystal silicon substrate and nitriding the surface of the single-crystal silicon substrate, thereby forming an interface layer of silicon nitride on the surface of the single-crystal silicon substrate; and forming a polycrystalline silicon film connected to the single-crystal silicon substrate by the interface layer.
Preferable aspects of a semiconductor device and a method for manufacturing the semiconductor device according to this invention are as follows. In a case where a single crystal silicon substrate is used as the single crystal semiconductor substrate and a polysilicon film is used as the polycrystalline semiconductor film, a silicon carbide film is used as the interface layer. The film thickness of the silicon carbide film is 10 nm or less.
Further, in a case where the polycrystalline semiconductor layer is formed in a trench, a method for first forming an amorphous semiconductor layer in the trench and then changing the amorphous silicon layer to a polysilicon film by the heat treatment may be used. In this case, since the heat treatment can also be used as the heat treatment effected in the post process, it is not necessary to newly add a heat treatment process for forming the polycrystalline layer and therefore the number of steps is not increased.
According to this invention, since the epitaxial growth from the single crystal semiconductor substrate to the polycrystalline semiconductor film can be suppressed and occurrence of transfer in the substrate can be prevented in the post process of high temperature after formation of the polycrystalline semiconductor film by forming the interface layer between the single crystal semiconductor substrate and the polycrystalline semiconductor film. Further, since the interface layer is conductive, an increase in the contact resistance between the single crystal semiconductor substrate and the polycrystalline semiconductor film can be suppressed.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.


REFERENCES:
patent: 5486706 (1996-01-01), Yuk

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