Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1997-01-27
2001-10-02
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S335000
Reexamination Certificate
active
06297532
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly to a semiconductor device which requires a high breakdown voltage, and a method of manufacturing the same.
2. Description of the Background Art
A semiconductor device of a type having a high breakdown voltage is characterized in that it has a high switching rate, operates safely over a large range, readily allows parallel operations, and so on. For these reasons, in recent years, attention is being paid to such semiconductor devices of the type having high breakdown voltages as well as to bipolar transistors and thyristors, as switching devices for power and the like.
As a conventional semiconductor device, a diode of a type having a high breakdown voltage will be described in the following.
FIG. 18A
is a cross sectional view schematically showing the structure of the conventional semiconductor device.
FIG. 18B
is a schematic plan view taken from the direction of arrow A
2
in FIG.
18
A.
Referring to
FIGS. 18A and 18B
, an n
−
epitaxial layer
3
and a p
+
diffused region
5
are formed on a surface of a p type semiconductor substrate
1
. This p
+
diffused region
5
forms an annular structure surrounding n
−
epitaxial layer
3
, when viewed two dimensionally.
An n
+
diffused region
7
is formed at a surface of n
−
epitaxial layer
3
.
On surfaces of n
−
epitaxial layer
3
and p
+
diffused region
5
, a silicon oxide film
9
is formed. A contact hole
9
a
exposing a portion of the surface of p
+
diffused region
5
, and a contact hole
9
b
exposing a portion of the surface of n
+
diffused region
7
, are formed at this silicon oxide film
9
.
A first electrode layer
11
is formed to be in contact with p
+
diffused region
5
through contact hole
9
a
. This first electrode layer
11
is formed to have an annular configuration along the contour of p
+
diffused region
5
when viewed two dimensionally. Also, a second electrode
13
is formed to be in contact with n
+
diffused region
7
through contact hole
9
b.
An interlayer insulating film
401
is formed, covering first and second electrode layers
11
and
13
. This interlayer insulating film
401
consists of a single layer of silicon oxide film, and is formed to have an approximately uniform film thickness T
1
. A thorough hole
401
a
is formed in interlayer insulating film
401
, reaching second electrode layer
13
. This through hole
401
a
includes a hole
401
b
opened by isotropical etching and a hole
401
c
formed by anisotropical etching. An interconnection layer
19
is formed to be in contact with second electrode layer
13
through this through hole
401
a
, being spaced apart from first electrode layer
11
with interlayer insulating film
401
therebetween.
In addition, n
+
diffused region
7
is formed by implantation of arsenic and p
+
diffused region
5
is formed by implantation of boron.
Here, n
−
means that the amount of n type impurity implanted is relatively small, and n
+
and p
+
means that the amount of n type and p type impurities implanted respectively is relatively large.
A method of manufacturing the conventional semiconductor device will now be described.
FIGS. 19
to
25
are schematic cross sections illustrating the method of manufacturing the conventional semiconductor device, in the order of the steps which are to be performed. Referring first to
FIG. 19
, n
−
epitaxial layer
3
is formed on the surface of p type semiconductor substrate
1
. On the surface of this n
−
epitaxial layer
3
, a thin silicon oxide film (not shown) is formed, which is patterned to a desired shape. Using this thin silicon oxide film as a mask, deposition of boron (B) is performed so that boron is diffused within n
−
epitaxial layer
3
. Thus, p
+
diffused region
5
is formed, surrounding n
−
epitaxial layer
3
in an annular configuration. The thin silicon oxide film is then removed.
Referring to
FIG. 20
, a thin silicon oxide film
421
is formed on the surface of n epitaxial layer
3
in which p
+
diffused region
5
has been formed. This thin silicon oxide film
421
is patterned by photolithography and etching to obtain a predetermined shape. Using this patterned silicon oxide film
421
as a mask, an n type impurity is implanted into n
−
epitaxial layer
3
. By diffusion and activation of this n type impurity, n
+
diffused layer
7
is formed at the surface of n
−
epitaxial layer
3
. Silicon oxide film
421
is then removed.
Referring to
FIG. 21
, silicon oxide film
9
is formed on the surfaces of n
−
epitaxial layer
3
and p
+
diffused region
5
. A photoresist
423
a
is applied on the entire surface of this silicon oxide film
9
, and then is subjected to exposure and development. In this way, resist pattern
423
a
having a hole pattern above p
+
diffused region
5
and above n
+
diffused region
7
is formed. Using this resist pattern
423
a
as a mask, silicon oxide film
9
is etched anisotropically, thereby forming contact holes
9
a
and
9
b
. From contact hole
9
a
, a portion of the surface of p
+
diffused region
5
is exposed. A portion of the surface of n
+
diffused region
7
is exposed through contact hole
9
b
. Thereafter, resist pattern
423
a
is removed.
Referring to
FIG. 22
, an AlSi (Aluminum Silicon) film is formed entirely on the surface of silicon oxide film
9
by sputtering. Then the Alsi film is patterned to a desired shape by photolithography and etching. In this way, first electrode layer
11
is formed to be in contact with p
+
diffused layer
5
through contact hole
9
a
and would present an annular configuration when viewed two dimensionally. At the same time, second electrode layer
13
is also formed, being in contact with n
+
diffused region
7
through contact hole
9
b.
Referring to
FIG. 23
, interlayer insulating film
401
consisting of a single layer of thick silicon film is formed entirely on the surface of silicon oxide film
9
by, for example, plasma such that it covers first and second electrode layers
11
and
13
with an approximately uniform film thickness.
Referring to
FIG. 24
, photoresist
423
b
is applied on an entire surface of interlayer insulating film
401
, and then is subjected to exposure and development. In this way, resist pattern
423
b
having a hole pattern above third electrode layer
13
is formed. Using this resist pattern
423
b
as a mask, an isotropic etching is performed on interlayer insulating film
401
. Thus, the surface of interlayer insulating film
401
which exposes itself at the bottom portion of the hole pattern is etched isotropically, and hole
401
b
is formed.
Thereafter, anisotropic etching is performed until the surface of second electrode layer
13
is exposed, still using resist pattern
423
b
as a mask. This etching leads to the formation of second hole
401
c
at the bottom portion of first hole
401
b
. These first and second holes
401
b
and
401
c
constitute through hole
401
a
. Resist pattern
423
b
is then removed.
Referring to
FIG. 25
, an AlSi (Aluminum Silicon) film
19
is formed entirely over the surface of first interlayer insulating film
401
by sputtering. This AlSi film
19
is patterned by photolithography and etching. This patterning leads to the formation of interconnection layer
19
which comes into contact with second electrode layer
13
via through hole
401
a
and is opposed to first electrode layer
11
with interlayer insulating film
401
therebetween.
In general, an industrial power supply line may be an alternating current line of either 200V or 400V. The 200V alternating current line is mainly employed in Japan, and the 400V alternately current line is mainly employed in Europe. When rectified, this alternating current of 200V becomes direct current of 300V, and the alt
Terashima Tomohide
Yamamoto Fumitoshi
McDermott & Will & Emery
Meier Stephen D.
Mitsubishi Denki & Kabushiki Kaisha
LandOfFree
Semiconductor device and method of manufacturing the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and method of manufacturing the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and method of manufacturing the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2575085