Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-07-10
2001-02-20
Meier, Stephen D. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S355000
Reexamination Certificate
active
06191461
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device including MOS transistors (insulated gate field-effect transistors), and more specifically, it relates to a structure for improving the electrostatic damage resistance of an output circuit for externally outputting signals.
2. Description of the Prior Art
FIG. 20
schematically illustrates the structure of an output circuit employed in a general semiconductor device. Referring to
FIG. 20
, the output circuit includes an output drive circuit
900
for generating a signal to be outputted in accordance with an internal signal, and an output circuit final stage
902
for outputting a signal to an output node
904
in accordance with the output signal from the output drive circuit
900
. The output node
904
is connected to an external pin terminal LP through a pad PD. The output circuit final stage
902
includes an n-channel MOS transistor N
1
which is connected between a power supply node and the output node
904
and conducts, when the output signal from the output drive circuit
900
is at a high level, for driving the output node
904
to a power supply voltage VDD level, and an n-channel MOS transistor N
2
which conducts, when the output signal from the output drive circuit
900
is at a high level, for discharging the output node
904
to the ground voltage level. Only one of these MOS transistors N
1
and N
2
conducts. In an output high impedance state, both of the MOS transistors N
1
and N
2
enter non-conducting states.
The output circuit final stage
902
is required to charge/discharge the output node
904
at a high speed. This output node
904
is connected to the external pin terminal LP through the pad PD, and the transistors N
1
and N
2
have relatively large current drivability due to the necessity for charging/discharging a large load at a high speed.
However, the output node
904
is connected to the external pin terminal LP through the pad PD, and equivalently connected with an LCR circuit formed by a high inductance component L, a parasitic capacitance C, wiring resistance and parasitic resistance R by wiring resistance of an external circuit. In case of charging/discharging such LCR circuit at a high speed, ringing is caused at the output node
904
and it takes a long time for stabilizing the output signal. In order to generate the output signal at a high speed with no ringing, the output circuit final stage
902
charges/discharges the output node
904
over a plurality of stages.
FIG. 21
illustrates an exemplary structure of a conventional multistage-drive output circuit final stage. This
FIG. 21
shows a circuit part for discharging the output node
904
. A circuit for pulling up the output node
904
to a high level may include a similar structure for multistage driving, appropriately depending on circuit characteristics of the output node
904
such as the dominance of overshoot or undershoot in the output node
904
.
Referring to
FIG. 21
, n-channel MOS transistors N
2
a
and N
2
b
are provided in parallel between ground node and the output node
904
. Conduction
on-conduction of MOS transistors N
2
a
and N
2
b
is controlled in accordance with control signals &phgr;
1
and &phgr;
2
respectively. In the structure of the conventional multistage-drive output circuit final stage, the n-channel MOS transistor N
2
of the output circuit final stage
902
shown in
FIG. 20
is split into the two MOS transistors N
2
a
and N
2
b
. These two MOS transistors N
2
a
and N
2
b
conduct at different timings, thereby preventing the output node
904
from rapid discharge. This discharge operation is now described with reference to a waveform diagram shown in FIG.
22
.
The control signal &phgr;
1
first rises from a low level to a high level so that the MOS transistor N
2
a
conducts for relatively slowly discharging the output node
904
. Then, the control signal &phgr;
2
rises from a low level to a high level, so that the MOS transistor N
2
b
conducts. Thus, the two MOS transistors N
2
a
and N
2
b
discharge the output node
904
, so that the voltage of the output signal rapidly falls to a low level. The control signal &phgr;
2
is activated at such a time that no undershoot is caused even by the rapid fall of the output signal from the output node
904
. The activation timings for the control signals &phgr;
1
and &phgr;
2
may be simply decided using a delay circuit, or activation of the control signal &phgr;
2
may be controlled in response to the voltage level of the output node
904
. In any case, the MOS transistors N
2
a
and N
2
b
for discharging the output node
904
conduct at different timings, thereby preventing rapid discharge of the output node
904
at a relatively high voltage level with a large discharge current. Alternatively, the voltage level of the output node
904
may be first reduced by high-speed discharge, and then the output node
904
is discharged at a low speed. Thus, the output signal can be stabilized at a faster timing with no undershoot.
The output node
904
is connected to the external pin terminal LP through the pad PD. The external pin terminal LP is connected to an external environment. Electrostatic discharge may be caused in the output node
904
through the external pin terminal LP. The cause for such electrostatic discharge may be the human body, a package insertion apparatus, a system operation or thunder. Such electrostatic discharge in the output node
904
may result in damage of gate insulating films of the MOS transistors N
1
and N
2
of the output circuit final stage
902
, or a large current flow (in amperes) caused by this electrostatic discharge may damage interconnection lines or P-N junctions. In order to prevent electrostatic discharge damage (ESD) caused by such electrostatic discharge, the output circuit final stage
902
must satisfy the specification value of ESD resistance. To this end, elements for improving the ESD resistance are added with respect to the output node
904
.
FIG. 23
schematically illustrates the planar layout of the output circuit final stage shown in FIG.
21
. Referring to
FIG. 23
, high-concentration N-type impurity regions
901
,
902
,
903
,
904
,
905
and
906
of low resistance are arranged alignedly with each other. Gate electrode layers
907
and
908
are arranged between the impurity regions
901
and
902
and between the impurity regions
902
and
903
respectively. Gate electrode layers
909
and
910
are arranged between the impurity regions
904
and
905
and between the impurity regions
905
and
906
respectively. The gate electrode layers
907
and
908
are connected to receive the control signal
41
, and the gate electrode layers
909
and
910
are connected to receive the control signal &phgr;
2
.
The impurity regions
901
and
903
are connected to the output node through contact holes CT, and the impurity region
902
is connected to a power supply node (ground node) through contact holes CT. The impurity regions
904
and
906
are connected to the output node through contact holes CT, and the impurity region
905
is connected to the power supply node (ground node) through contact holes CT.
The impurity regions
901
,
902
and
903
and the gate electrode layers
907
and
908
form the MOS transistor N
2
a
, and the impurity regions
904
,
905
and
906
and the gate electrode layers
909
and
910
form the MOS transistor N
2
b
. Two MOS transistors are connected in parallel with each other, to form each MOS transistor. Thus, a MOS transistor formed by the impurity regions
901
and
902
and the gate electrode layer
907
and that formed by the impurity regions
902
and
903
and the gate electrode layer
908
are connected in parallel with each other, thereby implementing the MOS transistor N
2
a
having high current drivability.
In order to improve electrostatic damage resistance against electrostatic discharge on the output node (the output node
904
shown in
FIG. 21
) connected with the MOS transistors N
2
a
McDermott & Will & Emery
Meier Stephen D.
Mitsubishi Denki & Kabushiki Kaisha
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