Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-09-07
2001-10-30
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C257S295000
Reexamination Certificate
active
06309968
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to methods and processes for forming integrated circuits on a semiconductor substrate. More particularly, this invention to methods and processes for forming dynamic random access memory (DRAM) to improve intrinsic refresh time and dichlorosilane formed gate oxide within a DRAM.
2. Description of the Related Art
The structure and fabrication of DRAM is well known in the art and shown in
FIG. 1. A
field oxide
115
is formed on the surface of a semiconductor substrate
100
. The field oxide
115
is etched to form openings for the electronic components that form the DRAM. A gate oxide
120
is formed within the opening. Heavily doped polycrystalline silicon is deposited on the gate oxide within the opening in the field oxide
115
to form the gate electrode
125
. The drain region
105
and the source region
110
are formed by the implantation of dopant atoms into the surface of the semiconductor substrate
100
in the opening in the field oxide
115
adjacent to the gate electrode
125
.
The gate oxide
120
is etched to form contact windows to the drain
105
and the source
110
. A metal such as tungsten or titanium is deposited at the contact window of the source and alloyed with the silicon at the surface of the semiconductor substrate to form the source contact
150
. The source contact is connected to the bit-line
155
of the DRAM. Generally, the bit-line
155
of the DRAM is formed of a heavily doped polycrystalline silicon.
The capacitor of the DRAM memory cell has a top plate
130
that is also formed of a heavily doped polycrystalline silicon. The top plate
130
of the capacitor is connected to the drain region by the drain contact
145
. The drain contact
145
is formed by the deposition and alloying with the silicon of a metal such as tungsten (W) or titanium (Ti) in the contact window that was formed as described above.
An insulating material such as a silicon dioxide or silicon nitride is deposited on the top plate
130
to form the capacitor dielectric
140
. The bottom plate
135
is formed by the deposition of a second layer of the heavily doped polycrystalline silicon. The bottom plate
135
is connected in common with the bottom plates of other memory cells and a reference power supply voltage source.
Layers of an interlayer dielectric serve to isolate the layers of the bit-lines
155
, the bottom plate
135
and the first metal layer
165
and the second metal layer
170
. The first and second metal layers
165
and
170
are formed by deposition of a metal such as aluminum on the surface of the interlayer dielectric
160
. The interlayer via
175
connects the first and second metal layers
165
and
170
. The first and second metal layers
165
,
170
and the layers of polycrystalline silicon such as the bit-lines
155
form the interconnections of the electronic components to make up integrated circuits such as the DRAM.
During the etching of the gate oxide
120
to form the contact openings to the drain
105
and the source
110
of the pass transistor of the memory cell, the surface of the semiconductor substrate
100
becomes damaged forming a path for leakage current
180
from the drain region
105
into the semiconductor substrate
100
. This leakage current decreases the time interval required for the intrinsic refresh of the DRAM memory cell.
To form the electrical contact for the bit-line to the gate
125
of the memory cell, a contact metal
190
is formed of an alloy of silicon and a metal such as tungsten. Dichlorosilane (SiH
2
CL
2
) is reacted with tungsten (W) to form the contact metal
190
as a tungsten silicide (WSi). During the reaction, chlorine ions (CL
2
) penetrate the heavily doped polycrystalline silicon of the gate
125
and are trapped
180
at the interface of the gate oxide
120
and the semiconductor substrate
100
. These trapped ions
180
decrease the reliability of the memory cell.
Processing for the VLSI Era, Volume
2
—Process Integration,
Wolf et al., Lattice Press, Sunset Beach, Calif. 1986, pp. 110-111 and quoted as follows describes sintering of contacts.
“The sintering or annealing of contacts (i.e., the alloying of contacts through treatment at an elevated temperature) is performed to allow any interface layer that exists between the metal and the Si to be consumed by a chemical reaction, and to allow the metal and Si to come into intimate contact through interdiffusion. The details of the various reactions that occur at specific metal-Si interfaces during the sinter cycle are described in the following sections examining the properties of each contact type. In this section we merely mention the several methods by which such intermixing of materials at the interface is performed.”
“The traditional method carries out the sinter step in a diffusion furnace, usually at 400-500° C. for 10 to 30 minutes in the presence of H
2
or a forming gas [a mixture of H
2
(5-10 at %) and N
2
(95-90 at %)]. Such gases are used because many metals are sensitive to oxygen at elevated temperatures, and because this step is also used to anneal out the surface states (i.e., interface traps at the oxide-Si interface) by tying up the dangling Si and oxygen bonds. The hydrogen is responsible for passivating and deactivating the interface traps.”
Further
Processing for the VLSI Era, Volume
1
—Process Technology,
Wolf et al., Lattice Press, Sunset Beach, Calif. 1986, pp. 221-223 describes as quoted below the properties of Si/SiO
2
interface and oxide traps.
“The interface trap charge, Q
it
refers to charge which is localized at the Si/SiO
2
interface on sites that can change their charge state by exchange of mobile carriers (electrons or holes) with the silicon. The charge state of the interface trap site changes with gate bias if the interface trap is moved past the Fermi level, causing its occupancy to change. These traps have energy levels distributed through out the silicon bandgap with a U-shaped distribution across the bandgap. The minimum level at midgap is typically the concentration level used to characterize their presence. The density of these charges is expressed as the number/cm
2
eV.”
Further, quoting from Wolf.
“In the low temperature post-metalization case, the sample is annealed in H
2
or other non-oxidizing ambients, such as forming gas (H
2
—N
2
) or Ar, in the temperature range of 350-500° C. for up to 30 min. Aluminum must be present for the anneal to be effective. Before such an anneal, a steam grown oxide may exhibit Q
it
densities in the low 10
11
cm
−2
eV
−1
range, while after anneal, the densities are decreased to the low 10
10
cm
−2
eV
−1
regime. This is an acceptable level for most device applications. It is believed that water in SiO
2
, present even in dry oxides, reacts with the aluminum to form Al
2
O
3
and atomic hydrogen (H). The H diffuses to the Si/SiO
2
interface, where it reacts chemically with traps, rendering them electrically inactive. If silicon nitride is present, it serves to block the diffusion of atomic H
1
and no reduction in Q
it
is observed. Thus postmetalization anneals should be performed prior to passivation, if Si
3
N
4
is used as the passivating overcoat.”
“In the case of the post oxidation high temperature anneal, the oxide is grown and then annealed at the growth temperature (in situ) in an H
2
or an inert ambient (N
2
or Ar). In this case, the reduction in Q
it
probably results from H
2
or trace quantities of H
2
O in the ambient, again promoting the reaction leading to atomic hydrogen.”
U.S. Pat. No. 4,151,007 (Levinstein et al.) describes adding a hydrogen heating (annealing) step to a MOS fabrication process at a point in the process after the last step that is to be performed at 600° C. or higher has been completed. The temperature at which hydrogen anneal step of the present invention is carried out is 650° C.≦950° C.
The inclusion of the hydrogen anneal step of Levinstein et al. significantly increases the stability of MOS structur
Chu Huey-Chi
Lin Yeh-Sen
Ackerman Stephen B.
Knowles Billy
Nelms David
Saile George O.
Vanguard International Semiconductor Corporation
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