Semiconductor device

Details Semiconductor device Semiconductor device

1997-05-20

2001-02-20

Clark, Sheila V. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Insulating material

C257S707000

Reexamination Certificate

active

06191476

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and to a fabrication method therefor. Moreover, the present invention relates to a substrate arrangement for driving a flat-plate light valve used for a direct-view display device and a projection-type display device.
More specifically, the present invention relates to a semiconductor integrated circuit substrate arrangement in which a group of pixel electrodes, a group of switches, and a group of driving circuit elements are formed on a single-crystal semiconductor silicon film on at electrical insulator. The substrate arrangement is integrated with, for example, a liquid crystal panel to constitute the so-called active-matrix arrangement.
Particularly, the present invention relates to a semiconductor device having a structure effective for minimizing the generation of heat in the semiconductor device or preventing the temperature of the semiconductor device from rising by releasing the heat from the semiconductor device when heat is generated.
An existing active-matrix arrangement is made by forming amorphous silicon or polycrystalline silicon on an electrical insulator such as a transparent glass substrate or transparent quartz substrate and further forming some or all of a group of picture element electrodes, a group of switching elements, and a group of driving circuit elements on the amorphous or polycrystalline silicon. However, it is not yet been successfully attempted to form all of the picture element group, switching element group, and driving circuit group on a single-crystal semiconductor film over an electrical insulator.
The substrate in which a semiconductor such as silicon is formed on an electrically insulating film is commonly called SOI (Silicon On Insulator), which is now recognized as a semiconductor device structure having a high operation speed and high integration density.
FIG. 2
shows a sectional view of a wafer having the SOI structure. In
FIG. 2
, reference symbol
21
is a single-crystal silicon substrate with a thickness of 500 to 1000 microns,
22
is a silicon oxide film with a thickness of over hundred angstroms to several microns,
23
is a single-crystal silicon film with a thickness of one hundred angstroms to several microns.
For a semiconductor integrated circuit made of an SOI wafer, the single-crystal silicon layer
23
on the electrical insulating film
22
is very thin. Therefore, when the integrated circuit comprises a complementary MIS transistor (complementary metal-insulator-semiconductor transistor; hereafter referred to as complementary MIS Tr), there are advantages that electric capacities between source and substrate, between drain and substrate, and between gate and substrate are decreased, the operation speed of the integrated circuit can be increased, a device isolation region between transistors can be formed very small, and the integration density can be increased as compared to when the integrated circuit is formed on a bulk single-crystal silicon wafer because the electric insulator
22
is present.
FIGS.
3
(
a
) to
3
(
d
) show a method for making single-crystal silicon on an existing insulating film using a method of bonding a single-crystal silicon layer with an oxidized single-crystal silicon layer.
In FIG.
3
(
a
), bulk single-crystal silicon
301
is thermally oxidized to form a silicon oxide SiO
2
layer
302
.
In FIGS.
3
(
b
) and
3
(
c
), the silicon with SiO
2
prepared in FIG.
3
(
a
) is bonded with the single-crystal silicon
303
at a high temperature.
In FIG.
3
(
d
), the thickness of the silicon
301
on whose surface SiO
2
is formed is decreased up to several microns or less through grinding or etching.
As shown in FIG.
3
(
d
), conventional SOI generally has a structure in which an SiO
2
layer
302
is present between thick single-crystal silicon
303
and thin single-crystal silicon
301
.
For an SOI wafer, because the insulating film
302
is present just under the thin single-crystal silicon
301
on which an integrated circuit is formed, the heat generated by the current flowing when the integrated circuit operates is not released to the thick conductive single-crystal silicon
303
under the insulating film
302
but it is collected in the thin single-crystal silicon layer
301
and serves to raise the temperature of the thin single-crystal silicon layer with the passage of time.
When the integrated circuit comprises a complementary MIS Tr, the current flowing through the transistor increases and the temperature elevation rate also increases if the transistor size is decreased to increase the integration density.
If the temperature of thin single-crystal silicon layer rises, carrier trap levels are easily generated in a gate insulator of the MIS transistor, causing transistor characteristic fluctuation, and degrading the integrated circuit reliability.
FIG. 4
is a sectional view showing another embodiment of a semiconductor device. The sectional view in
FIG. 4
shows an N-type metal-oxide semiconductor field-effect transistor (hereafter referred to as MOS Tr) formed on poycrystalline silicon (hereafter referred to as Poly-Si) on an insulating substrate.
Reference numeral
401
is a transparent substrate made of glass or quartz,
402
and
403
are a source and drain containing N-type impurities at a high concentration of approx. 1×10
19
to 1×10
20
cm
−3
respectively, and
404
is a P-well region containing little or few impurites or containing impurities at a low concentration of about 1×10
16
cm
−3
.
The source
402
, drain
403
, and P-well
404
are formed in Poly-Si. Symbols
405
and
406
are silicon oxide SiO
2
formed by oxidizing Poly-Si containing the source
402
, drain
403
, and P-well
404
. The SiO
2
405
of these two silicon oxide films SiO
2
serves as a gate insulator of an N-type MOS Tr.
Symbol
407
is Poly-Si containing N-type impurities at a high concentration of approx. 1×10
20
cm
−3
, which serves as a gate of a MOS Tr. An N-type MOS Tr comprises the source
402
, drain
403
, P-well
404
, gate insulator
405
, and gate,
407
. Symbol
408
is an intermediate insulating film formed by depositing a silicon oxide,
409
is a source electrode made of aluminum, and
410
is a drain electrode made of aluminum. The intermediate insulating film
408
is removed from portions where the source electrode
409
contacts the source
402
and the drain electrode
410
contacts the drain
403
. Symbol
411
is a passivation film made of a silicon nitride film or silicon oxide.
Also for an existing semiconductor having the sectional structure shown in
FIG. 4
, the transparent insulating substrate
401
under the N-type MOS Tr is an insulator and the intermediate insulating film
408
and the passivation film
411
above the N-type MOS Tr are insulating films. Therefore, the heat produced when current flows through the N-type MOS Tr formed in Poly-Si is hardly released from the Poly-Si.
For the structure of a transistor made of amorphous silicon (hereafter referred to as a-Si) formed on the transparent insulating substrate mainly used for a display device though not illustrated, an insulating substrate is present under the transistor and an insulating film such as a passivation film is present above it. Therefore, the heat generated when a current flows through the transistor is not released from the transistor but it is easily collected in the transistor.
In recent years, the size of a transistor (hereafter referred to as Tr) constituting an integrated circuit formed on single-crystal silicon has been continually decreased. For example, when the integrated circuit comprises a complementary metal-oxide-semiconductor transistor (hereafter referred to as CMOS Tr), the length of the Tr is already decreased to 1 &mgr;m or less, and moreover a length of 0.2 to 0.3 &mgr;m has recently been realized.
FIG. 5
shows a sectional view of a semiconductor which is a sectional view of an N-type MOS Tr formed in single-crystal silicon.
Reference numeral
501

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