Transistor with ultra shallow tip and method of fabrication

Details Transistor with ultra shallow tip and method of fabrication Transistor with ultra shallow tip and method of fabrication

1997-11-17

2001-12-04

Wojciechowicz, Edward (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S019000, C257S065000, C257S336000, C257S382000, C257S377000, C257S385000, C257S742000, C257S755000, C257S773000, C438S062000, C438S065000, C438S131000, C438S231000, C438S272000, C438S278000, C438S290000, C438S327000, C438S334000, C438S277000

Reexamination Certificate

active

06326664

ABSTRACT:

The structure of a conventional MOS transistor
100
is shown in FIG.
1
. Transistor
100
comprises a gate electrode
102
, typically polysilicon, formed on a gate dielectric layer
104
which in turn is formed on a silicon substrate
106
. A pair of source/drain extensions or tip regions
110
are formed in the top surface of substrate
106
in alignment with outside edges of gate electrode
102
. Tip regions
110
are typically formed by well-known ion implantation techniques. Formed adjacent to opposite sides of gate electrode
102
and over tip regions
110
are a pair of sidewall spacers
108
. A pair of source/drain regions
120
are then formed, by ion implantation, in substrate
106
substantially in alignment with the outside edges of sidewall spacers
108
.
As the gate length of transistor
100
is scaled down in order to fabricate a smaller transistor, the depth at which tip region
110
extends into substrate
106
must also be scaled down (i.e., decreased) in order to improve punchthrough characteristics of the fabricated transistor. Unfortunately, the length of tip region
110
, however, must be larger than 0.10 &mgr;m to insure that the later, heavy dose, deep source/drain implant does not swamp and overwhelm tip region
110
. Thus, in the fabrication of a small scale transistor with conventional methods, as shown in
FIG. 1
, the tip region
110
is both shallow and long. Because tip region
110
is both shallow and long, tip region
110
exhibits substantial parasitic resistance. Parasitic resistance adversely effects (reduces) the transistors drive current.
Thus, what is needed is a novel transistor with a low resistance ultra shallow tip region with a VLSI manufacturable method of fabrication.
SUMMARY OF THE INVENTION
A novel transistor with a low resistance ultra shallow tip region and its method of fabrication is described. According to the preferred method of the present invention, a gate dielectric layer is formed on a first surface of a semiconductor substrate. Next, a gate electrode is formed on the gate dielectric layer. Then a first pair of sidewall spacers are formed adjacent to opposite sides of the gate electrode. Next, a pair of recesses are formed in the semiconductor substrate in alignment with the outside edges of the first pair of sidewall spacers. Next, a semiconductor material is selectively deposited into the recesses such that the semiconductor material extends both above and below the first surface of the semiconductor substrate. Dopants are then diffused from the semiconductor material into the substrate beneath the first pair of sidewall spacers to form an ultra shallow tip region. A second pair of sidewall spacers are then formed on semiconductor material adjacent to the outside edges of the first pair of sidewall spacers. Next, a deep implant is made in alignment with the outside edges of the second pair of sidewall spacers to form a deep junction source/drain contact region. Finally, silicide is formed onto the source/drain regions and gate electrode of the fabricated transistor.


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Disclosed Anonymously; “Method for Making Devices having Reduced Field Gradients at Junction Edges”; Jul., 1989, No. 303, New York, US; 2244 Research Disclosure; pp. 496.
Momose, et al.; “Tunneling Gate Oxide Appraoch to Ultra-High Current Drive in Small-Geometry MOSFETS”;International Electron Devices Meeting 1994 IEEE; Dec. 11-14, 1994; pp. 25.1.1-25.1.4.
Mark Rodder, Member,IEEE, and D. Yeakley; “Raised Source/Drain MOSFET with Dual Sidewall Spacers”;8179 IEEE Electron Device Letters12(1992) Mar., No. 3, New York, US; pp. 89-91.

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