Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-03-12
2001-02-20
Saadat, Mahshid (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S355000, C257S356000, C257S361000
Reexamination Certificate
active
06191455
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semi-conductor device. More to particularly this invention relates to a semi-conductor device having an electrostatic protection device for protecting from electrostatic discharge damage as to silicon large scale integrated circuit (LSI) at which an epitaxial substrate is in use.
DESCRIPTION OF THE PRIOR ART
In the semiconductor device, a rated value thereof exists. The semiconductor device should not be used while exceeding the defined rated value. When the semiconductor device is used while exceeding the rated voltage, characteristic of the semiconductor device is changed or the semiconductor device itself is broken. However, in some cases, a surge which is sudden electric pulse exceeding the rated voltage is applied to the semi-conductor device.
Under the circumstances, various protection methods are proposed for protecting the semi-conductor device from the surge. “VLSI ELECTRONICS MICROSTRUCTURE SCIENCE Vol. 22” by Anant. G. Sabnis discloses prior technology for protecting the semi-conductor device from the surge. There is explained the protection technology from the surge referring to this document.
According to the prior technology, an internal transistor of LSI is protected by an electrostatic protection device from the surge applied to an outer terminal. As shown in
FIG. 1A
, in a metal-oxide semiconductor large scale integrated circuit (MOS LSI), it causes a protection device to be provided at an input terminal in order to prevent fluctuation of transistor characteristic caused by application of surge to gate oxide film of an internal circuit directly, or breakdown of the gate oxide film. Namely, diodes
81
,
82
are connected in between the outer terminal and VDD, and in between the outer terminal and ground (GND) respectively. It causes charge generated by application of the surge to discharge through these diodes. Thereby these diodes function as devices which causes stress to the gate oxide film of the internal transistor to ease. On the other hand, with respect to an output terminal, a drain junction of an output transistor T
80
accomplishes a role of protection device.
Further, as shown in
FIG. 1B
, in logic LSI which is typical of gate array, gate control type diodes
83
,
84
whose protective effect is higher than the diode are used as a protection device of the input terminal. The gate control type diodes
83
,
84
utilize a MOS transistor. The control gate terminal of the NMOS type transistor
84
is connected to the GND, while the control gate terminal of the PMOS type transistor
83
is connected to the VDD. Forward characteristic thereof is identical with above-described diode, while reverse characteristic is that it causes breakdown to be done at lower voltage (BVds) than that of the above-described diode. Thereby the protective effect to the surge is enhanced. Furthermore, in the NMOS type transistor whose source terminal is connected to the GND to form MOS constitution so that the protection device becomes ON-state at further low voltage while utilizing snap back phenomena, thereby it causes protective effect to the surge to further enhanced.
On the other hand, it is necessary to cause gate oxide film to be thin film for operating LSI in more high speed, or for enhancing integration degree of LSI. However, surge resistance property of the gate oxide film becomes weak with reduction of thickness of gate oxide film. Above-described protection devices
83
, and
84
are of MOS construction, thus there are problems that leak current increases and breakdown occurs easily while applying surge to gate oxide film of the protection device. Furthermore, an output transistor T
80
combined with role of protection device, although breakdown does not occur, there is a problem that circuit operation is influenced by fluctuation of characteristic caused by charge injection into gate oxide film.
As the method for resolving the above-described problems, “Internal ESD Transients in Input Protection Circuits IEEE/IRPS 1989” by Y. Fong and C. Hu discloses construction in which field transistor is added to conventional protection device. As shown in
FIG. 2A
, field transistor (Thick Field Device, TFD)
90
is inserted in between the above-described conventional protection devices (Field Plate Diode, FPD)
91
,
92
and input pad
93
. While in relation to output transistor, as shown in
FIG. 2B
, field transistor (TFD)
95
is inserted in between two output transistors of PMOS type transistor
96
and NMOS type transistor
97
, and output pad
98
.
Next,
FIG. 3
is a cross sectional view showing construction of the conventional field transistor. The transistor is a parasitic bipolar transistor with adjoined N
+
diffusion layer region
31
separated by device isolation oxide film
4
as an emitter and a collector respectively, and with P-well
2
as a base. A controlling electrode enveloping the device isolation oxide film
4
is connected to the collector. The N
+
diffusion layer region
31
and source region and drain region of the NMOS transistor are formed simultaneously, and NMOS transistor is formed on the P-well
2
. Metal silicide
10
for lowering resistance is formed on the surface of the N
+
diffusion layer region
31
and on the surface of the gate electrode
6
of the NMOS transistor. Here, reference numeral
5
denotes gate oxide film,
6
denotes gate electrode,
7
denotes side wall oxide film,
9
denotes N
+
SD region,
11
denotes substrate interlayer insulation film,
12
denotes embedded electrode,
13
denotes wiring electrode, and
30
P-type substrate.
Next, protection effect in relation to surge of the conventional semiconductor device is explained referring to
FIGS. 2A
,
2
B, and
3
. When, for example, positive surge voltage is applied to the input pad
93
or the output pad
98
, shown in FIG.
2
. Protection device or output transistors
96
,
97
in next part are protected by escaping surge while causing the parasitic bipolar transistor to be ON-state in between collector-emitter. While in relation to negative voltage application, it is capable of escaping charge to the P-well
2
in regard to value of bias more than Vf, because diode in between collector and P-well comes into forward bias.
As described above, in the electrostatic protection device using the conventional field transistor, it is capable of protecting gate oxide film of the internal circuit or the gate control type diode by causing the field transistor to be ON.
However, protection effect of the semiconductor device is still insufficient. Enlargement of the effect thereof is required. In the conventional semiconductor device, in order to enlarge the protection effect there is a method that it causes charge accompanied with surge to flow easily while increasing area of the field transistor. There is a method that the semi-conductor device has a device construction in which transistor is easy to come into ON-state. However, with regard to the first method which opposes direction of making LSI smaller. There are problems that large influence to circuit characteristic with enlargement of parasitic capacitance occurs, thus reducing operation margin. With regard to the second method, it becomes necessary to enhance injection efficiency of carrier from emitter to base while lowering density of the P-well
2
.
However, in order to render LSI microscopic, it becomes necessary to enhance density of well as represented by scaling law. Further, enhancement of density for the well is a technology which is necessary to realize microscopic device isolation. Consequently, to enhance injection efficiency of carrier from emitter to base while lowering density of P-well is contrary to microscopic LSI. Although it is capable of lowering effective impurity density of only P-well of the field transistor forming section by implementing ion implantation of N-type impurity to the P-well while adding PR (photo resist) process in manufacturing process of the field transistor, in this method, there is a proble
Eckert II George C.
NEC Corporation
Saadat Mahshid
Sughrue Mion Zinn Macpeak & Seas, PLLC
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