Method of patterning dielectric

Details Method of patterning dielectric Method of patterning dielectric

1998-04-14

2001-02-20

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S637000, C438S640000, C438S672000, C438S673000

Reexamination Certificate

active

06191028

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims priority benefit of Taiwan application Serial no. 86118145, filed Dec., 3, 1997, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a method of patterning a dielectric layer, and more particularly to a method of patterning a dielectric layer with a low dielectric constant k.
2. Description of the Related Art
In the semiconductor fabrication process, as the dimension of devices on a chip becomes smaller and smaller, the density of interconnect pitch is higher and higher. For a common dielectric layer, for example, a silicon oxide layer, due to the high dielectric constant, a high RC delay is easily caused. Therefore, this kind of dielectric layer is not used as an inter-metal dielectric (IMD) in a high speed IC any longer. To apply a low k dielectric layer has the advantage such as reducing the interconnection parasitic capacitance, consequently reducing the RC delay, or mitigating the cross talk between metal lines, hence, the operation speed is improved. Hence, the low k dielectric layer is a very popular IMD material used in a high speed IC.
A common low k dielectric layer comprises organic polymers, for example, flare and parylene which are very suitable for used as an IMD.
FIG. 1A
to
FIG. 1D
show the process of fabricating metal interconnects. Over a substrate
10
having a metal wiring layer
11
formed thereon, a dielectric layer
12
is formed, or example, using chemical vapour deposition (CVD) or spin-on-glass (SOG) to deposit organic polymer with a thickness of about 3000 Å to 10000 Å. An insulation masking layer
13
such as a silicon oxide layer is formed on the dielectric layer
12
as a hard mask for the subsequent etching process. The insulation masking layer
13
is formed, for example, by CVD with silane (SiH
4
) and oxygen, and tetra-ethyl-oxy-silicate (TEOS) as reacting gas. Using photolithography, a photo-resist layer
14
is formed and patterned on the insulation masking layer
13
.
Referring to
FIG. 1B
, using the photo-resist layer
14
as a mask, the insulation masking layer
13
and the dielectric layer
12
are etched to form an opening
12
and to expose the metal wiring layer
11
.
Referring to
FIG. 1C
, using a plasma containing oxygen as a cleaning agent, the photo-resist layer
14
is removed. Similar to the material contained in the photo-resist layer
14
, the material contained in the photo-resist layer
14
has a large proportion of carbon. Thus, the dielectric layer
12
is removed while removing the photo-resist layer
14
.
Referring to
FIG. 1D
, after removing the photo-resist layer, a bowing side wall
16
is formed within the opening
15
. In the subsequent process for forming conductive material, the step coverage is affected by the formation of the bowing side wall. Therefore, the stability and reliability of the devices are degraded.
In the he above method, the formation of a low k dielectric layer
12
in the process of interconnection has quite a few disadvantages. While removing the photo-resist layer
14
, since the dielectric material is very similar to the photo-resist material, for example, both containing a large proportion of carbon, part of the low k dielectric layer
12
within the opening
15
is removed too. A bowing side wall
16
is thus formed within the opening
15
. The bowing side wall
16
causes difficulty during the subsequent deposition process, and therefore, a poor step coverage is resulted. The conductivity for interconnects and the stability for devices are degraded. The degradation is more obvious as the dimension of and distances between devices becomes smaller and smaller.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a method patterning a dielectric layer. The disadvantage of easily etched by plasma containing oxygen is improved. Therefore, it is more advantageous for the fabrication of interconnects.
To achieve these objects and advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed towards a method of patterning a dielectric layer. On metal wiring layer formed on a provided substrate, a dielectric layer is formed. A masking layer is formed on the dielectric layer. A cap insulation layer is formed and patterned to form an opening on the masking layer, and the opening is aligned with the metal wiring layer. The masking layer and the dielectric layer are etched, so that the opening is deepened and the metal wiring layer is exposed. A conductive layer is formed over the substrate to fill the opening.
To achieve these objects and advantages, and in accordance with the purpose of the invention, another method of patterning a dielectric layer is disclosed. On a metal wiring layer formed on a provided substrate, a first dielectric layer, a first masking layer and a first cap insulation layer are formed in sequence. A first opening aligned with the metal wiring layer is formed by etching the first cap insulation layer, so that the underlying first masking layer is exposed. The exposed first masking layer is etched to expose the first dielectric layer. A second dielectric layer, a second masking layer and a second cap insulation are formed over the substrate in sequence. A second opening is formed by etching the second cap insulation, so that the second masking layer is open within the second opening. The exposed second masking layer and the underlying second dielectric layer etched, and the first dielectric is etched by using the second cap insulation layer as a mask until the metal wiring layer is exposed. A conductive layer is formed over the substrate.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
patent: 5328553 (1994-07-01), Poon
patent: 5506177 (1996-04-01), Fiordalice et al.
patent: 5578523 (1996-11-01), Fiordalice et al.
patent: 5602060 (1997-02-01), Kobayahi et al.
patent: 5702568 (1997-12-01), Shin et al.
patent: 5897375 (1997-10-01), Watts et al.
Wolf “silicon Processing for the VLSI Era” vol. 1, pp. 547-551, 555-556, 1986.
Wolf “Silicon Processing for the VLSI Era” vol. 1, pp. 547-551, 555-556, 1986.

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