Electrical computers and digital processing systems: memory – Address formation – Generating a particular pattern/sequence of addresses
Reexamination Certificate
1998-04-06
2001-10-09
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Generating a particular pattern/sequence of addresses
C711S005000, C711S157000, C365S230040, C345S519000
Reexamination Certificate
active
06301649
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a semiconductor memory device and a method of reading data from and writing data into the semiconductor memory device, and particularly to a memory device of a type wherein a method of reading data therefrom and writing data therein is contrived.
DESCRIPTION OF THE RELATED ART
One arbitrary screen of a CRT used for a general TV or panel or a PC (Personal Computer) is made up of a plurality of lines scanned over a fluorescent screen of a Braun tube in a transverse direction thereof. In the conventional system, one line comprises image information units (hereinafter called “pixels”) of about 900 dots to 1000 dots. The number of lines constituting one screen commonly ranges from about 500 to 600. When a memory is used in a system (TV, CRT or the like) which handles image information, it is necessary to access line information at high speed. On the other hand, the line information is easy to treat with because of serial addresses to be incremented. Therefore, when one attempts to handle the line information in a commonly general-purpose DRAM (Dynamic Random Access Memory), a page mode for accessing a series of pieces of memory information selected by an arbitrary word line at high speed is often used.
Memories used except for the general-purpose DRAM include a field memory, a dedicated memory called “frame memory.” These memories are capable of connecting a data register corresponding to one page to its corresponding bit line pair of the DRAM, transferring a series of plural memory information selected by a corresponding word line of the DRAM to their corresponding data register (or transferring write-completed data register information to a series of plurality of memories selected by their corresponding word lines) and providing a quick serial access. Thus, even the field memory or the frame memory serially accesses information (i.e., page information corresponding to one row) coupled to the same word line in a page mode as in the case of the aforementioned DRAM. Namely, a page mode (corresponding to a page mode (Enhanced Data Out: EDO) faster in speed in the recent DRAM) has heretofore been used in an image processing system using a TV and a CRT when used to access the line information.
The conventional page mode is used for various purposes such as a scan converter requiring an access (i.e., a serial access in a column direction) in a vertical direction, a noise filter, a matrix calculation, etc. In the conventional memory, however, the serial access in the column direction cannot be structurally performed at high speed although the serial access in the row direction can be executed at high speed. In the general-purpose DRAM, for example, an access clock frequency ranges from 15 ns to 20 ns upon an EDO mode corresponding to the present highest speed serial access mode (page access mode). However, since time is required between the rise to fall of a word line when it is desired to perform the serial access in the column direction, the access clock frequency results in a range of 120 ns to 150 ns.
A synchronous DRAM (or SDRAM), which has to come into wide use recently, mostly takes a configuration in which memory units called “separately-accessible banks” are provided in plural form. A two-bank configuration is commonly used for the synchronous DRAM. Data on word lines (i.e., rows different from each other) different from each other every serial bit in a row direction can be taken out by using the two banks. However, even the memory having the two-bank configuration cannot obtain serial access to different word line information every bit. Since a succession of page access in a row direction is basically defined as a basic operation even in the case of the field memory used as a TV-dedicated memory, a high-speed serial access in a column direction cannot be implemented.
Thus, a plurality of line memories are electrically connected to a memory to realize a serial access in a column direction in an actually-available system. Namely, a problem arises in that attached parts called the line memories are needed and thereby the system will lead to an increase in cost.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a memory device allowing only memories capable of providing quick serial access in a row direction to obtain quick serial access in a column direction without having to use other attached parts, and a method of writing data into and reading data from the memory device.
In the present invention, memory banks each having memory cells arranged in an X and a Y directions, Y decoder for selecting Y-direction addresses of the memory cells and X decoder for selecting X-direction addresses of the memory cells are predicated on a memory having n (where n: natural numbers) memory banks operable independent from one another.
Items of data specified by a (where a: natural numbers) continuous X addresses and having the same Y addresses are successively written into or read from the memory cells arranged in the X direction, which are specified by X addresses corresponding to 1+knth (where k=0, 1, 2, . . . ) in one of the banks. After all the data have been written into or read from the specified memory cells, the corresponding data are successively written into or read from the memory cells specified by X addresses corresponding to 2+knth (where k=0, 1, 2, . . . ) in another one of the banks.
Typical ones of various inventions of the present application have been shown in brief. However, the various inventions of the present application and specific configurations of these inventions will be understood from the following description.
REFERENCES:
patent: 5497351 (1996-03-01), Oowaki
patent: 5561777 (1996-10-01), Kao et al.
patent: 5598374 (1997-01-01), Rao
patent: 5781201 (1998-07-01), McCormack et al.
patent: 5815169 (1998-09-01), Oda
patent: 5924111 (1999-07-01), Huang et al.
1997 DRAM Data Book, Micron Technology Inc., pp. 1-1, 1-3, 1-4, and 1-7, Mar. 1997.
Jones Volentine PLLC
OKI Electric Industry Co., Ltd.
Portka Gary J.
Yoo Do Hyun
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