Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
1999-04-16
2001-02-20
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S696000, C438S733000
Reexamination Certificate
active
06191041
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88103373, filed Mar. 5, 1999.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of manufacturing an integrated circuit. More particularly, the present invention relates to a method of fabricating a semiconductor device.
2. Description of Related Art
At present, photolithography is a core technique that determines the integrated circuit process integration. Photolithographic steps determine the definition of patterns for all the thin layers relating to the structure of semiconductor devices. Thus, photolithography is a determining key factor in the further of minimization of semiconductor devices.
For example, metal oxide semiconductor (MOS) is widely applicable to the process of very large scale integration (VLSI) circuits at the present. First, the process forms an isolating structure for the devices in the substrate to prevent carriers from passing through the substrate and moving among the adjacent devices. Then an oxide layer and a conducting layer are formed on the substrate, and a layer of photoresist is formed to cover the conducting layer with conventional photolithographic patterning. The pattern on the mask is shifted to a photoresist in exposing and patterning steps. Next, an etching process is performed to define patterns of the oxide layer and the conductive layer with a photoresist serving as an etching mask. This enables the oxide layer and the conducting layer that remain to form a gate oxide layer and a gate layer in the active area defined by the isolating structure. After that, dopants are implanted into in the substrate to form a source/drain region, with the gate layer serving as a mask.
In the above method, the dimension of the gate is determined by the photoresist after exposing and patterning, while 248 nm deep ultra-violet ray is used as the exposing light source for performing a 0.25 &mgr;m process in the industry today. If a process is to be performed below 0.18 mm, a stepper is required to enable further minimization of the device, such as an improved KrF 248 nm scanning stepper with improved lens quality, an advanced mask and wafer platform technique, and a high numerical aperture. But the wavelength is physically limited while the mask difficult to manufacture. Moreover, the improvement via a photolithographic system to meet the demand of the photolithographic process of below 0.18 mm also increases the cost of the process.
SUMMARY OF THE INVENTION
The present invention is to provide a method of fabricating a semiconductor device, in which a masking layer which has an opening pattern on a material layer is formed and a mask spacer on a sidewall of the opening is formed. The opening is filled with an insulating layer to cover the material layer exposed by the opening. After that, the mask layer and the mask spacer are removed, so that the insulating layer that remains serves as a mask for defining the material pattern. After the material layer uncovered by the insulating layer is removed, the insulating layer is then removed to expose the patterned material layer.
As embodied and broadly described herein, the method can be applied to the pattern definition of the conducting layer of the gate. The above material layer can be a polysilicon layer, while the masking layer, the mask spacer, and the insulating layer have different etching and polishing ratios from those of the polysilicon layer. The material for the masking layer and the mask spacer includes silicon nitride, while the material for the insulating layer includes silicon oxide. The method is to cover the substrate fully with a silicon oxide layer. Then, the oxide layer covering the surface of the masking layer and the mask spacer is removed, so that the oxide layer that remains covers only the material. exposed by the above opening. The opening of the above masking layer, the size of the opening can be determined according to the current photolithographic process. The deficiency in photolithographic process can compensate for the mask spacer formed on the sidewall of the opening. This allows the reduction of the dimension of material layer after patterning. Therefore, the difficulty of the photolithography process is reduced, and the dimension of the material layer to be defined is reduced. This improves the degree of the device integration.
Another method of fabricating a semiconductor device is provided in the invention, in which a masking layer having opening pattern on the material layer is formed and a mask spacer is formed on the sidewall of the opening. A part of the material layer exposed in the opening is removed, extending the opening to the material layer. The opening is filled with an insulating layer to cover the material layer exposed by the opening. The masking layer and the masking spacer are removed, so the insulating layer that remains serves as a mask for defining the material pattern. The material layer uncovered by the bottom of the insulating layer is removed. Ultimately, the insulating layer is removed to expose the patterned material layer.
As embodied and broadly described herein, the method is applicable to the pattern definition of a conducting layer of the gate. The above material layer can be the polysilicon layer, while the masking layer and the masking spacer have different etching and polishing ratios from those of the polysilicon layer. The material for the masking layer and the mask spacer includes silicon nitride, while the material for the insulating layer includes silicon oxide. Initially, the substrate is covered with an oxide layer in full scale. The oxide layer covering the masking layer and the surface of the mask spacer is removed via chemical mechanical polishing (CMP), so that the remaining oxide layer covers only the top of the material layer exposed by the above opening. The masking layer and the mask spacer are removed by wet etching. The planarization process can be selectively performed with CMP to remove the excessive material layer, leaving only the insulating layer in the opening of the material layer. In the present invention, the size of the opening can be determined according to the current photolithographic process. The deficiency in the photolithographic process can be compensated for by the mask spacer formed on the sidewall of the opening, so that the dimension of material layer is reduced after patterning. Therefore, the difficulty encountered in the photolithographic process is reduced by the method of the invention, and the dimension of the defined material layer is reduced. This improves the degree of the device integration.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 4942137 (1990-07-01), Sivan et al.
patent: 5381040 (1995-01-01), Sun et al.
patent: 5767017 (1998-06-01), Armacost et al.
patent: 5970354 (1999-10-01), Hause et al.
Chen Kin-Chan
Huang Jiawei
J C Patents
United Microelectronics Corp.
Utech Benjamin L.
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