Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-10-01
2001-11-13
Nguyen, Tuan H. (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S649000, C438S592000
Reexamination Certificate
active
06316362
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device including a metal suicide layer having a high melting point metal overlying a semiconductor substrate, more in detail, to the method for manufacturing the semiconductor device of high reliability having the silicide layer of excellent thermal stability.
(b) Description of the Related Art
A silicide process is frequently used to manufacture a semiconductor device, and a variety of the suicide processes have been conventionally practiced. One of these silicide processes is described in JP-A-9(1997)-069497.
In the silicide process described therein, a field oxide film
401
is formed on a semiconductor substrate
400
by means of a known lithographic process and a known selective oxidation process as shown in FIG.
1
A. Then, a gate oxide film
402
and a gate polysilicon layer
403
are sequentially grown on the active area surrounded by the field oxide film
401
.
Then, a gate electrode
404
is formed by patterning the gate polysilicon layer by employing a photolithographic process and a dry etching method as shown in FIG.
1
B.
A side wall
405
made of a silicon oxide film is formed on the side surface of the gate electrode
404
by employing a chemical vapor deposition (CVD) technique and an etching technique. An N-type gate electrode or a P-type gate electrode
406
is then formed by a photolithographic process, and a P-type diffused layer or an N-type diffused layer
407
is formed by an ion implantation process.
After a spontaneous oxide layer on the N-type or P-type gate electrode
406
and the P-type or N-type diffused layer
407
is removed and a cobalt layer having a thickness of 10 nm is formed on the semiconductor substrate
400
at a temperature of, for example, to 450° C. by sputtering in a vacuum ambient, the substrate is heated for 5 minutes in the vacuum ambient, thereby forming a Co
2
Si film having a thickness of about 15 nm on positions where the cobalt film and the silicon are in contact with each other.
Thereafter, in a nitrogen atmosphere, the Co
2
Si film is converted into a CoSi film having a thickness of 20 nm through phase transition by rapid thermal annealing (RTA) at 500° C. for 30 seconds.
The cobalt film left unreacted on the dielectric film is selectively removed by wet-etching with a mixed aqueous solution containing sulfuric acid and hydrogen peroxide. The wafer is then subject to the rapid thermal annealing at 800° C. for 10 seconds in a nitrogen atmosphere to conduct phase-transition from the CoSi film to a Co
2
Si film
408
having a thickness of about 35 nm as shown in FIG.
1
C.
Since the surfaces of the gate electrode and the diffused layer are self-aligned to form the silicide in accordance with the above silicide process, a high-speed semiconductor device can be realized due to low resistance wiring.
The silicide process has an advantage of selective silicidation only in a desired Area.
With the advance of miniaturization and high integration of semiconductor devices, a so-called system-on-chip (SOC) device such as having a DRAM and a logic device on a single chip has an increasing demand.
In order to realize the SOC device, a variety of problems associated therewith must be solved. In order to mount a DRAM and a logic device on a single chip, a DRAM part and a logic part which are generally manufactured by processes entirely different from each other should be manufactured in common processes to decrease the number of fabrication steps and alleviate the complexity of the fabrication steps.
A method of forming suicide layers on the gate electrodes and the diffused layers of the DRAM part and the logic part in a self-aligning manner is employed for solving the above problems.
This process is called a salicide (self-aligned silicide) process which is widely utilized for a purpose of realization of transistors having high performance and high integration used in a logic device.
This process enables simultaneous or sequential formation of the DRAM part and the logic part to simplify the steps and to reduce the number of the steps.
However, in this process, a new problem arises. Even when the silicides are simultaneously formed on the gate electrodes and the diffused layers of the DRAM part and the logic part, formation of capacitors in the DRAM is ordinarily conducted after the formation of the silicide of the gate electrode.
Since a high temperature treatment is conducted in the capacitor forming step after the formation of the silicide film, the silicide film is coagulated during the capacitor forming step to increase the resistance thereof and has poor heat resistance.
SUMMARY OF THE INVENTION
In view of the foregoing, an object of the present invention is to provide a method for manufacturing a semiconductor device having a silicide film of excellent heat resistance and high reliability.
The present invention provides a method for manufacturing a semiconductor including the steps of: forming a gate electrode layer made of polysilicon or amorphous silicon overlying a semiconductor substrate; forming a gate electrode by etching the gate electrode layer; forming a side wall on a side surface of the gate electrode, consecutively ion-implanting and heat-treating, the gate electrode and a surface portion of the semiconductor substrate to form the gate electrode as an N-type or P-type gate electrode and to form the surface portion as a diffused layer; forming a metal silicide layer on the N-type or P-type gate electrode and the diffused layer.
The present invention can be modified by the step of ion-implantation into the gate electrode and/or the step of thermally treating the gate electrode.
In accordance with the method for manufacturing the semiconductor device, the ion-implantation and/or the thermal treatment of the gate electrode and the diffused layer to optimize the surface impurity concentration thereof enables to improve the heat resistance of the metal silicide film formed on the gate electrode and the diffused layer, thereby providing a semiconductor device having high reliability.
The above and other objects, features and advantages of the present invention will be more apparent from the following description.
REFERENCES:
patent: 4378628 (1983-04-01), Levinstein et al.
patent: 5482895 (1996-01-01), Hayashi et al.
patent: 5780361 (1998-07-01), Inoue
patent: 6150248 (2000-11-01), Sekiguchi et al.
patent: 6156615 (2000-12-01), Kepler
patent: 6197646 (2001-03-01), Goto et al.
patent: 3-67334 (1991-10-01), None
patent: 7-115198 (1995-05-01), None
patent: 7-193237 (1995-07-01), None
patent: 7-211903 (1995-08-01), None
patent: 7-283168 (1995-10-01), None
patent: 9-69497 (1997-03-01), None
patent: 10-242079 (1998-09-01), None
patent: 10-335265 (1998-12-01), None
Lai et al., “A Novel Process to Form Cobalt Silicided P+ POly-Si Gates By BF2+ Implantation Into Bilayered CoSi/a-Si Films and Subsequent Anneal”, IEEE Electron Devices Lett., vol. 19, p-159 (1998).*
Juang et al., “Shallow Junctions Formed by BF2+ Implantation into Thin CoSi Films and Rapid Thermal Annealing”, Appl. Phys., vol. 76, p. 323 (1994).*
Cheng et al., “A Silicidation-Induced Process Consideration for Forming Scale-Down Silicided Junction”, IEEE Electron Device Lett., vol. 15, No. 9, p. 342 (1994).*
Chen et al., “Thermal Stability and Dopant Drive-OUt Characteristics of Cosi2 Polycide Gates” J. Appl. Phys., vol. 73, p. 4712 (1993).
Foley & Lardner
NEC Corporation
Nguyen Tuan H.
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