Low power, high speed level shifter

Details Low power, high speed level shifter Low power, high speed level shifter

2000-12-19

2001-10-23

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S068000

Reexamination Certificate

active

06307398

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to integrated circuits and in particular the present invention relates to voltage level translators fabricated thereon.
BACKGROUND OF THE INVENTON
There are instances in integrated circuit design where voltage level translators are needed to interface between circuits requiring different voltage levels. For example, many integrated circuits such as DRAMs operate in a voltage range <4 volts, but require voltage swings >4 volts to interface with external circuits or provide signals to other circuits included with the DRAM.
Two primary objectives of any voltage level translator are the reduction in time required to translate an input signal and the power requirements to complete the translation. A CMOS voltage translator described in U.S. Pat. No. 5,136,190 entitled “CMOS Voltage Translator Circuit” issued to Chern et al., addresses these two objectives. The Chern et al. patent describes a circuit which provides an interface between circuitry where control signals are between Vcc and V.s. to circuits using signals between Vcc′ and V.s.. Specifically, the Chern et al. level translator works in integrated circuits where Vcc is <4 and Vcc′ is >4 volts.
Although the Chern et al. patent provides a fast, efficient level translator, it fails to address interfaces requiring voltage swings between a supply voltage (Vcc) and some higher voltage (Vccp). That is, Chern et al. describes a level translator which translates an input voltage swing from ground (V.s.) to supply (Vcc) into an output voltage swing from V.s. to Vccp. This translator is relatively slow and wastes power in interfacing with a circuit which requires an input voltage swing between Vcc and Vccp. It can be seen that the transition time and power required to move the output voltage between V.s. and Vcc is an unnecessary use of resources.
For the reason stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an integrated circuit voltage level translator which can translate an input voltage signal into an output voltage signal where the minimum output voltage level is substantially equal to the maximum input voltage level.
SUMMARY OF THE INVENTION
The above mentioned problems with voltage level translators and other problems are addressed by the present invention and which will be understood by reading and studying the following specification. A level translator is described which provides an output voltage between ground and a lower voltage Vbb.
In particular, the present invention describes a voltage level translator comprising an input connection receiving an input signal having a first upper voltage level and a first lower voltage level, an input stage producing first and second intermediate outputs. The first intermediate output being at substantially the first upper voltage level when the input signal is at substantially the first lower voltage level. The second intermediate output being at the first upper voltage level when the input signal is at the first upper voltage level. The voltage level translator further comprises an output stage producing an output signal in response to the input signal, the output signal being at a second lower voltage level when the first intermediate output is at substantially the first upper voltage level, and at the first lower voltage when the second intermediate output is at substantially the first upper voltage level. The output stage comprises a first n-channel transistor having its gate connected to the first intermediate output, its source electrically connected to the second lower voltage level, and its drain connected to a source of a second n-channel transistor. The second n-channel transistor has its gate connected to the second intermediate output, and its drain electrically connected to the first lower voltage level. The output stage further comprises an output line connected to the drain of the first n-channel transistor.


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