Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-01-10
2001-12-04
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185190, C365S185220, C365S185230
Reexamination Certificate
active
06327183
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed to an apparatus and method to program a memory cell.
RELATED ART
FIG. 1
illustrates a cross sectional view of a conventional memory transistor, also known as a memory cell. The memory transistor includes a control gate CG, a floating gate FG, a drain D, a source S, and a well W. Thin oxide layers isolate the floating gate FG from the control gate CG as well as the well W.
FIG. 2
schematically illustrates a conventional NAND type flash memory array
100
that includes numerous memory cells, each depicted in
FIG. 1. A
“string” includes a selection transistor T
i−1
, memory transistors M
i−1
to M
i−j
, and a selection transistor T
i−2
, all being serially coupled. Each string can be coupled to a bit line BLj and a common source CS through selection transistors T
i−1
and T
i−2
, respectively. The control gates for selection transistors T
i−1
and T
i−2
are respectively connected to selection lines Sl
1
and Sl
2
. The control gates for the memory transistors M
i−1
to M
i−j
are respectively connected to word lines W
1
to W
j
. Typically, a read operation is performed on a page basis, i.e., flash memory cells coupled to a word line are read together.
Herein, a memory transistor represents logical LOW when it is programmed to have a threshold voltage that is larger than a predetermined minimum threshold voltage for logical LOW bits. Correspondingly, a memory transistor represents a logical HIGH when it is erased to have a threshold voltage that is less than a predetermined maximum threshold voltage for logical HIGH bits. One skilled in the art will understand that logic level assignments to the predetermined minimum and maximum threshold voltages are arbitrary.
A large variation in the programming and erasing characteristics of individual NAND type flash memory transistors among a memory array is common. The variations can be due to structural differences, which cause difference in threshold voltage characteristics. Such variations introduce differences in programming and erasing speeds among memory transistors. Conventional NAND type flash memory arrays use fixed programming and erase voltages that cannot adjust to programming and erasing characteristics of the memory transistors. Some memory transistors in flash memory arrays do not respond to the fixed programming and erase voltages of NAND type flash memory arrays. Accordingly, NAND type flash memory arrays that include an intolerably high number of non-responsive memory cells are typically discarded. As such, the yield of usable NAND memory arrays fluctuates. Low yield increases the manufacturing cost of NAND memory, and hence leads to a less profitable and less competitive position.
Thus what is needed is a method and apparatus to adaptively control the programming and erase voltages of NAND type flash memory and thereby increase the proportion of usable memory cells.
SUMMARY
In one embodiment of the present invention, a voltage control circuit that programs memory cells comprises a voltage output circuit that generates nonlinearly incremented programming voltages.
In another embodiment of the present invention, a voltage control circuit that programs a memory cell comprises an output terminal, a first impedance source, a second impedance source, and a comparator. The output terminal provides the programming voltages to the memory cell. The first impedance source is coupled to the output terminal and the second impedance source is coupled to the first impedance source. The second impedance source comprises a plurality of impedance elements where the impedance elements are selectively coupled to increase the impedance level of the second impedance source nonlinearly. The comparator is coupled to the first impedance source and the second impedance source. The comparator controls the output terminal to provide the programming voltages.
In another embodiment of the present invention, a method that programs a memory cell with nonlinearly incremented programming voltages comprises applying a first program pulse defined at least by a first voltage to the memory cell, applying a second program pulse defined at least by a second voltage to the memory cell, and applying a third program pulse defined at least by a third voltage to the memory cell. In this embodiment, the difference between the third voltage and the second voltage is less than the difference between the second voltage and the first voltage.
It is believed that nonlinearly incremented programming voltages may produce a tighter distribution of threshold voltages of the memory cells, thereby increasing the read margin, i.e., the threshold voltage difference, between logical LOW and logical HIGH bits. It is also believed that nonlinearly incremented programming voltages may subject the memory cells to lower programming voltages and improve the reliability of memory devices over time.
Various embodiments of the present invention will be more fully understood in light of the following detailed description taken together with the accompanying drawings.
REFERENCES:
patent: 5299162 (1994-03-01), Kim et al.
patent: 5410511 (1995-04-01), Michiyama
patent: 5523972 (1996-06-01), Rashid et al.
patent: 5528546 (1996-06-01), Chao et al.
patent: 5553020 (1996-09-01), Keeney et al.
patent: 5600593 (1997-02-01), Fong
patent: 5621687 (1997-04-01), Doller
patent: 5661685 (1997-08-01), Lee et al.
patent: 5677885 (1997-10-01), Roohparvar
patent: 5734609 (1998-03-01), Choi et al.
patent: 5740107 (1998-04-01), Lee
patent: 5751637 (1998-05-01), Chen et al.
patent: 5784316 (1998-07-01), Hirata
patent: 5798547 (1998-08-01), Urai et al.
patent: 5801989 (1998-09-01), Lee et al.
patent: 5812457 (1998-09-01), Arase
patent: 5844840 (1998-12-01), Le et al.
patent: 5852576 (1998-12-01), Le et al.
patent: 5880996 (1999-03-01), Roohparvar
patent: 5892710 (1999-04-01), Fazio et al.
patent: 5909393 (1999-06-01), Tran et al.
patent: 5920508 (1999-07-01), Miyakawa et al.
patent: 5926409 (1999-07-01), Engh et al.
patent: 5946231 (1999-08-01), Endoh et al.
patent: 5949714 (1999-09-01), Hemink et al.
patent: 5953255 (1999-09-01), Lee
patent: 5959883 (1999-09-01), Brennan, Jr. et al.
patent: 5963476 (1999-10-01), Hung et al.
patent: 5969987 (1999-10-01), Blyth et al.
patent: 6011715 (2000-01-01), Pasotti et al.
patent: 6014330 (2000-01-01), Endoh et al.
patent: 6040996 (2000-03-01), Kong
patent: 6052306 (2000-04-01), Sedlak et al.
patent: 6088281 (2000-07-01), Miyakawa et al.
Derhacobian Narbeh
Han K. Michael
Pawletko Joseph G.
Advanced Micro Devices , Inc.
Hsia David C.
Kwok Edward C.
Nguyen Viet Q.
Skjerven Morrill & MacPherson LLP
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