Electrical computers and digital processing systems: support – Clock control of data processing system – component – or data...
Reexamination Certificate
1997-10-20
2001-02-27
Lee, Thomas C. (Department: 2787)
Electrical computers and digital processing systems: support
Clock control of data processing system, component, or data...
C714S723000
Reexamination Certificate
active
06195759
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed to a method and apparatus for operating a synchronous strobe bus. More particularly, the present invention is directed to a method and apparatus for dynamically balancing a synchronous strobe bus.
BACKGROUND OF THE INVENTION
Devices in computer systems typically communicate with each other using a bus. In many computer systems, when a sending device outputs data on a bus, it simultaneously outputs a clock or “strobe” that informs a receiving device when the data on the bus can be read. Buses that are accompanied by a strobe are referred to as “synchronous strobe buses.”
FIG. 1
is a block diagram illustrating communication using a synchronous strobe bus between two computer devices: a chipset
10
and a graphics controller
12
. A data bus
14
exchanges data between devices
10
and
12
. Data bus
14
is typically a bidirectional multi-bit bus (e.g., a 16-bit data bus). A strobe line
16
carries a strobe signal from device
10
to device
12
, and vice versa. The strobe signal indicates when data on data bus
14
can be read by device
10
or device
12
.
FIG. 2
is a timing diagram illustrating data
20
on data bus
14
in relation to a strobe signal
22
on strobe line
16
. The data
20
between a first transition of data bus
14
at time To and a second transition at time T
2
is “D
0
” (i.e., the bits on data bus
14
, when read by devices
10
or
12
, form D
0
). Between the second transition at time T
2
and a third transition at time T
4
, data
20
is “D
1
”.
Devices
10
and
12
read data
20
on data bus
14
when strobe signal
22
transitions from high to low, or from low to high. Therefore, in
FIG. 2
, data
20
is read at time T
1
and at time T
3
.
When implementing synchronous strobe buses, there is a need to have an adequate setup and hold time. The setup time, “T
su
” (between T
0
and T
1
and between T
2
and T
3
in FIG.
2
), is the time from when data
20
is initially valid (i.e., can be read by a receiving device) to the time strobe signal
22
transitions. The hold time “T
hold
” (between T
1
and T
2
in FIG.
2
), is the time from when strobe signal
22
transitions until the time data
20
is no longer valid.
The setup time and hold time for a given window are inversely related. Specifically, when the setup time is increased, the hold time is decreased, and vice versa. In order to optimally position the strobe signal
22
relative to the data
20
signal, it is desirable for the setup time to equal the hold time. This is referred to as “balancing” the setup time and hold time. A balanced setup and hold time provides for a maximum error margin on either side of a transitioning strobe signal
22
.
However, the setup time and hold time can vary depending on the number of bits that are toggled on data bus
14
, and the type of toggles (i.e. either a 1 to 0 toggle or a 0 to 1 toggle). For example, because of incremental delay induced by simultaneous switching outputs, as more bits are toggled on data bus
14
, it takes longer for all the bits on data bus
14
to be in condition to be read by a receiving device. Therefore, when the number of bits toggled is increased, the setup time is decreased and the hold time is increased.
A problem with prior art devices that include a synchronous strobe bus is that the strobe signal
22
is typically adjusted so that the setup time is balanced with the hold time when one bit of data
20
is toggled. However, when more than one bit is toggled, the setup time is decreased, and the setup time and hold time are no longer balanced. Because the setup time and hold time in prior art devices are not always in balance, these devices must either maintain a larger setup and hold time or contend with a smaller margin of error. However, it is desirable to reduce the setup and hold time as much as possible because the frequency of the devices can be increased as the setup and hold times are decreased.
Based on the foregoing, there is a need for a method and apparatus for operating a synchronous strobe bus with a reduced setup and hold time compared to the prior art.
SUMMARY OF THE INVENTION
One embodiment of the present invention is a computer system device. The computer system device includes a data bus that transmits a plurality of bits of data, and a strobe line. The computer system device further includes a strobe signal generator that generates a strobe signal, and a variable delay device that couples the strobe signal generator to the strobe line. The variable delay device selectively delays the strobe signal.
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patent: 4594654 (1986-06-01), Maniar et al.
patent: 4649299 (1987-03-01), Yamanouchi
patent: 5062485 (1991-11-01), Wesson et al.
patent: 5280587 (1994-01-01), Shimodaira et al.
patent: 5311520 (1994-05-01), Raghavachari
patent: 5341371 (1994-08-01), Simpson
patent: 5423076 (1995-06-01), Westergren et al.
patent: 5557782 (1996-09-01), Witkowski et al.
patent: 5761735 (1998-06-01), Huon et al.
patent: 5857095 (1999-01-01), Jeddeloh et al.
Intel Corporation
Kenyon & Kenyon
Lee Thomas C.
Omar Omar A.
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