Semiconductor memory device having an address exchanging...

Details Semiconductor memory device having an address exchanging... Semiconductor memory device having an address exchanging...

1998-11-09

2001-02-27

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230060, C365S225700

Reexamination Certificate

active

06195299

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory that identifies a defective area address in advance and avoids the defective area address during use.
2. Description of Related Art
As the capacity of semiconductor memories has increased, production yield has decreased. Consequently, a memory has been proposed which seeks to avoid a defective address in use. This type of semiconductor memory is disclosed in Japanese Kokai No. 8-102529, which corresponds to U.S. Pat. No. 5,596,542.
The attached
FIG. 1
shows a layout drawing of a cell array of this first example of prior art. A DRAM uses a double word-line structure comprising a main word line and a sub-word line. Therefore, a word line is selected in accordance with an X (low) address in a main word decoder column
401
and sub-word decoder column
402
.
FIG. 2
shows the circuit diagram of the main word decoder of the first prior art. In the main word decoder, one end of a fuse
501
is connected to the inputs of an n-channel MOS transistor M
3
and inverter INV
24
. The other end of the fuse
501
is connected to a power supply terminal Vcc. The output of the inverter INV
24
is input to the gate electrode of the nMOS transistor M
3
, one input of an AND circuit and the gate electrode of an nMOS transistor M
1
. The nMOS transistors M
1
and M
2
control the potential of a precharged roll-call signal RCX. The output of an inverter INV
21
for inverting a block selection signal BSL is connected to the other inputs of the AND circuit. Address signals X
4
TX
5
Tn and X
2
TX
3
Tn are input to a NAND circuit. The output of the NAND circuit is input to a first NOR circuit NOR
1
together with the inverted signal of a block selection signal BSL. The output of the first NOR circuit NOR
1
is input to a second NOR circuit NOR
2
together with the output of the AND circuit. Moreover the output of the first NOR circuit NOR
1
is input to the gate electrode of the nMOS transistor M
2
for controlling the roll-call signal RCX. The output of the first NOR circuit NOR
1
is connected to a main word line MWL through an inverter INV
22
and an inverter (driver) INV
23
driven by a boosted power supply voltage VBOUT. The output of the second NOR circuit NOR
2
is connected to a main word line MWLB.
By disconnecting the fuse
501
, a word line connected to the main word line MWL output from the main word decoder and a memory cell connected to the word line are disabled. Whether the fuse
501
is disconnected can be read from the outside through a roll-call test. In the roll-call test mode, it is detected whether the roll-call signal RCS connected in accordance with the wired OR logic is dropped to a low level. The user of the DRAM of this conventional example first performs the roll-call test and enters the X address of a defective cluster (a cluster is constituted of a plurality of sectors) in a defective-address table before using the DRAM.
It has also been proposed to convert a defective address and use it as a ¼-capacity memory in order to salvage damaged production and to prevent yield from decreasing. This is disclosed in Japanese Kokai No. 7-85696.
FIG. 3
shows a block layout drawing of this second prior art. The second prior art have a double-line structure comprising a main word line and a sub-word line.
FIG. 4
shows a block diagram of the address-system circuit of the second prior art.
In the case of the second prior art, the X address is determined by the 10 bit address X
0
to X
9
, and the Y address is determined by the 10 bit address Y
0
to Y
9
. Address bits X
9
and Y
9
are the most-significant address bits. The inside of the memory is divided into four regions by the most-significant address bits, X
9
and Y
9
. As shown in
FIG. 3
, if a defective cell is present in blocks containing (X
9
, Y
9
)=(0, 0) and (0, 1), the address is converted by the address conversion circuit of
FIG. 4
so that the block containing (1, 0) is physically selected when (X
9
, Y
9
)=(0, 0) is input. Moreover, the three other blocks are disabled and shipped as ¼-capacity memories.
In the case of a storage device such as a hard disk, input and output buses use the same wiring in order to decrease the number of bus wirings. Thus, a bus using a common input and output, inputs the first sector address and the number of sectors to be continuously accessed with a command in order to improve the bus utilization efficiency and thereafter, an operation mode for transferring only input/output data is prepared. In the case of this operation mode, the bus utilization efficiency is improved because it is unnecessary to input a command for each sector. However, when a defective cluster is present and sector addresses are not continued, it is impossible to use the continuous-access operation mode.
The first prior art has a problem that the throughput of data is deteriorated because the continuous access mode cannot be used if a defective cluster is present. The second prior art has another problem that capacity is greatly decreased because the capacity is decreased to ¼. Moreover, a simple address conversion can cause address duplication of a previously defective address and a non-defective address.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a novel semiconductor memory device that avoids the above problem of the prior art.
It is another object of the present invention to provide a semiconductor memory having a wide continuously-accessible region and a high effective data transfer rate.
It is another object of the present invention to exchange a defective address for a non-defective address without greatly increasing either the number of circuit elements or the chip area, wherein an address exchange is performed simply by inverting an address in a decoder, and an address exchanging circuit is located at the intersection between a main word decoder and a column decoder.
These and other objects of the present invention will be more apparent to those of skill in the art from the following detailed specification and accompanying figures.


REFERENCES:
patent: 5373471 (1994-12-01), Saeki et al.
patent: 5596542 (1997-01-01), Sugibayashi et al.
patent: 5623640 (1997-04-01), Nakabo
patent: 5625596 (1997-04-01), Uchida
patent: 5889712 (1999-03-01), Sugibayashi
patent: 7-85696 (1995-03-01), None
patent: 8-102529 (1996-04-01), None

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