Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-08-17
2001-05-29
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S623000, C438S624000, C438S637000, C438S788000
Reexamination Certificate
active
06239016
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same, and more specifically to a multilevel interconnection in a semiconductor device and a method for forming the same.
2. Description of Related Art
With an increased integrated density and an elevated operation speed of the semiconductor device, microfabrication of an interconnection layer has become remarkable. Therefore, since a fine pattern is formed, a capacitance between interconnections of the same level increases, with the result that the characteristics of the semiconductor device is significantly deteriorated. This capacitance between interconnections will be called a “line-to-line capacitance” in this specification.
In order to reduce the line-to-line capacitance, it was proposed to use an insulator film of a lower dielectric constant. For example, Japanese Patent Application Pre-examination Publication No. JP-A-62-005643, (the content of which is incorporated by reference in its entirety into this application, and also an English abstract of JP-A-62-005643 is available from the Japanese Patent Office and the content of the English abstract of JP-A-62-005643 is also incorporated by reference in its entirety into this application), proposes to form a cavity between adjacent interconnections of the same level, thereby to reduce the line-to-line capacitance. This example is shown in FIG.
1
A.
Furthermore, Shin-Puu Jeng, et al. “A Planarized Multilevel Interconnect Scheme With Embedded Low-Dielectric-Constant Polymers For Sub-Quarter-Micron Applications”, 1997 Symposium on VLSI Technology Digest of Technical Papers, pp. 73-74, (the content of which is incorporated by reference in its entirety into this application) proposes to form an organic film of a lower dielectric constant only between adjacent interconnections of the same level. This example is shown in
FIG. 1B
In
FIGS. 1A and 1B
, Reference Numeral
1
designates a substrate, and Reference Numeral
2
indicates an insulator layer formed on the substrate
1
. Reference Numeral
3
shows lower level interconnections
3
formed on the insulator layer
2
, and Reference Numerals
4
a
and
4
b
denote insulator films formed to cover the lower level interconnections
3
. Reference Numeral
5
designates a cavity formed between adjacent lower level interconnection
3
, and Reference Numeral
6
indicates a metal pillar extending through the insulator films
4
a
and
4
b
to contact with a target one of the lower level interconnection
3
. Reference Numeral
7
shows upper level interconnections formed on the insulator film
4
b,
and one of the upper level interconnections
7
is connected to the metal pillar
7
. Reference Numeral
8
denotes an organic film
8
, and Reference Numeral
10
designates a hollow formed in the metal pillar
7
.
In these prior art examples, if the spacing between interconnections is on the order of sub-microns or less, the metal pillar
6
for electrically connecting the upper level interconnection
7
and the lower level interconnection has often become formed to deviate from the lower level interconnection
3
, so that a portion of the metal pillar
6
extends into a region between two adjacent lower level interconnections
3
.
As a result, in the example shown in
FIG. 1A
, the metal pillar
6
reaches the cavity
5
in a deviated portion of the metal pillar
6
, so that a gas retained in the cavity
5
is discharged to create the hollow
10
in the metal pillar
6
. This results in an increased resistance of a connection resistance and in a lowered reliability. Alternatively, the metal pillar
5
is formed to fill up the cavity
5
between the lower level interconnections
3
, which results in an increased leak current between the lower level interconnections
3
.
In addition, in the example shown in
FIG. 1B
, the metal pillar
6
contacts with the organic film
8
in a deviated portion of the metal pillar
6
, so that because of a degasification of the organic film
8
, the hollow
10
is formed in the metal pillar
6
. Similarly, this results in an increased resistance of a connection resistance and in a lowered reliability.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which have overcome the above mentioned defects of the conventional ones.
Another object of the present invention is to provide a multilevel interconnection in a semiconductor device in which a metal pillar for connecting interconnections of different levels is stably formed by forming between adjacent interconnections of the same level, an insulator having a lower dielectric constant, such as a cavity and an organic film having a lower dielectric constant, other than a silicon oxide film, and by forming the metal pillar in no contact with the insulator having the lower dielectric constant.
Still another object of the present invention is to provide a method for forming the above mentioned multilevel interconnection in the semiconductor device.
The above and other objects of the present invention are achieved in accordance with the present invention by a semiconductor device including first level interconnections and second level interconnections separated from each other by an interlayer insulator film, and a connection member for electrically connecting one of the first level interconnections and one of the second level interconnections to each other, wherein a capacitance reducing insulator is formed between adjacent first level interconnections to reduce a line-to-line capacitance in the first level interconnections, and a separation film is formed to surround the capacitance reducing insulator so as to isolate the connection member from the capacitance reducing insulator film.
The capacitance reducing insulator can be formed of air, an insulating gas, an insulating liquid, an insulating organic material, an insulating inorganic material excluding a silicon oxide, or a porous insulator.
According to another aspect of the present invention, there is provided a method for forming a semiconductor device including first level interconnections and second level interconnections separated from each other by an interlayer insulator film, and a connection member for electrically connecting one of the first level interconnections and one of the second level interconnections to each other, the method including:
a step for forming first level interconnections on an insulator layer;
a capacitance reducing step for forming a capacitance reducing insulator between adjacent first level interconnections and a separation film on the insulator layer to surround the capacitance reducing insulator but in contact with the first level interconnections;
an interlayer insulator film forming step for forming an interlayer insulator film to cover the separation film, for insulating between the first level interconnections and possible second level interconnections;
a connection step for forming a hole to penetrate through the interlayer insulator film and to reach one of the first level interconnections while avoiding the capacitance reducing insulator surrounded by the separation film and filling up the hole with a conductive material; and
a step for forming second level interconnections on the interlayer insulator film so that one of the second level interconnections is in contact with the conductive material filled in the hole and therefore the one of the second level interconnection is electrically connected to the one of the first level interconnections.
For example, the capacitance reducing step is achieved by growing the separation film between the first level interconnections on the insulator layer by means of a plasma chemical vapor deposition process applying a high frequency electric field, so that, as the capacitance reducing insulator, a cavity is simultaneously created in the separation film between adjacent first level interconnections.
The interlayer insulator film for
Chaudhuri Olik
Eaton Kurt
Foley & Lardner
NEC Corporation
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