CMOS level shift circuit for integrated circuits

Details CMOS level shift circuit for integrated circuits CMOS level shift circuit for integrated circuits

1999-08-31

2001-07-10

Kim, Jung Ho (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C327S390000, C326S063000, C326S081000

Reexamination Certificate

active

06259299

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a level shift circuit for use in integrated circuits and, more particularly, to a CMOS level shift circuit.
BACKGROUND OF THE INVENTION
The manufacturing techniques of semiconductor devices have been gradually advancing. As such, integrated circuits have been proportionally affected.
The internal circuitry of an integrated circuit often operates at different power source voltages (e.g., 3V and 5V).
FIG. 1
is a schematic diagram of a conventional CMOS level shift circuit for an integrated circuit. The CMOS level shift circuit generally includes an inverter circuit having a PMOS transistor PM
1
and an NMOS transistor NM
1
. The PMOS transistor PM
1
has a source coupled to a power source voltage V
CC2
(e.g., 5V), a drain coupled to an output terminal
30
, and a gate coupled to an input terminal
10
. The NMOS transistor NM
1
has a drain coupled to the output terminal
10
, a source coupled to a ground voltage V
SS
. (e.g., 0V), and a gate coupled to the input terminal
10
. The gates of the PMOS transistor PM
1
and the NMOS transistor NM
1
are coupled to each other. Here, the power source voltage V
CC2
is an operating voltage of the internal circuitry of the integrated circuit.
When the low voltage (e.g., 0V) is input to the input terminal
10
, the low voltage is applied to the gate of the PMOS transistor PM
1
and the NMOS transistor NM
1
. Accordingly, the PMOS transistor PM
1
is on and the NMOS transistor NM
1
is off, so that the power source voltage V
CC2
is applied to the output terminal
30
through the PMOS transistor PM
1
.
On the other hand, when the high voltage (e.g., 3V) is input to the input terminal
10
, the high voltage is applied to the gate of the PMOS transistor PM
1
and the NMOS transistor NM
1
. Thus, the NMOS transistor NM
1
is on, and the PMOS transistor PM
1
is weakly on in a static state due to a voltage difference between the gate voltage (e.g., 3V) of the PMOS transistor PM
1
and the power source voltage V
CC2
(e.g. 5V). Therefore, a current path is formed between the power source voltage V
CC2
and the ground voltage V
SS
, so that a leakage current flows into the inverter circuit via the undesired current path of the PMOS transistor PM
1
.
Accordingly, there is a problem in the conventional CMOS level shift circuit shown above in that power consumption of the conventional CMOS level shift circuit may occur when the high voltage (e.g., 3V) is input to the input terminal
10
. As the voltage difference between the gate voltage (e.g., 3V) of the PMOS transistor and the power source voltage V
CC2
(e.g., 5V) is increased in the static state, the power consumption also increases in proportion thereto.
SUMMARY OF THE INVENTION
The present invention is directed to a level shift circuit for an integrated circuit. The level shift circuit ofthe present invention advantageously includes a charge/discharge circuit capable of receiving an input voltage which is different from a power source voltage applied to internal circuitry ofthe integrated circuit. Moreover, the level shift circuit advantageously prevents a leakage current from flowing into an inverter circuit included in the level shift circuit.
According to an aspect ofthe present invention, a level shift circuit is provided which includes an input terminal for receiving a logic input signal changing between a first voltage and a reference voltage. An output terminal provides a logic output signal changing between a second voltage and the reference voltage. A pull-up transistor has a control electrode and a pair of controlled electrodes. The controlled electrodes are coupled between the second voltage and the output terminal. A pull-down transistor has a control electrode and a pair of controlled electrodes. The control electrode of the pull-down transistor is coupled to the input terminal, and the controlled electrodes of the pull-down transistor are coupled between the reference voltage and the output terminal. A charge/discharge circuit charges the control electrode ofthe pull-up transistor with the second voltage when the logic input signal is changed from the reference voltage to the first voltage. The charge/discharge circuit discharges the control electrode ofthe pull-up transistor to the reference voltage when the logic input signal is changed from the first voltage to the reference voltage.
The charge/discharge circuit includes a first switching device coupled between the second voltage and the control electrode of the pull-up transistor for supplying the second voltage to the control electrode of the pull-up transistor when the output signal is equal to the reference voltage. The first switching device inhibits the supply of the second voltage to the control electrode ofthe pull-up transistor when the output signal is equal to the second voltage.
The charge discharge circuit also includes a second switching device coupled between the input terminal and the control electrode of the pull-up transistor for supplying the control electrode voltage ofthe pull-up transistor to the reference voltage in response to the reference voltage. The second switching device inhibits the supply of the control electrode voltage of the pull-up transistor to the reference voltage in response to the first voltage.
The first switching device is a PMOS transistor, and the second switching device is an NMOS transistor. A channel of the PMOS transistor is less a channel of the NMOS transistor. The pull-up transistor is a PMOS transistor, and the pull-down transistor is an NMOS transistor.


REFERENCES:
patent: 5493245 (1996-02-01), Kao et al.
patent: 5646563 (1997-07-01), Kuo
patent: 5650742 (1997-07-01), Hirano
patent: 5912577 (1999-06-01), Takagi
patent: 6001290 (1999-12-01), Avery et al.
patent: 6133757 (2000-10-01), Huang et al.

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