Static information storage and retrieval – Addressing – Multiple port access
Reexamination Certificate
1998-04-28
2001-02-13
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Multiple port access
C365S154000, C365S189040, C365S189050
Reexamination Certificate
active
06188633
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to registers used in computer processors. More specifically, the present invention relates to register write operations and the organization and configuration of word lines in registers.
DESCRIPTION OF THE RELATED ART
In the art of computing, registers are used within a processor for temporary storage of variables. A collection of such registers is known in the art as a register file. Typically, a register file includes a plurality of read and write ports to allow multiple operands to be written to and read from the register file in a single clock cycle.
Computer systems perform tasks by executing instructions, and the speed of a computer system is largely determined by the rate at which instructions are executed. One technique used by computer designers to increase the instruction execution rate is to include multiple execution units, with each execution unit capable of executing instructions in parallel with the other units. To support additional execution units, the register file must have sufficient read and write ports to allow the execution units to access the register file concurrently. Since many instructions read two or more operands from the register file and write a single operand, it is common for register files to have more read ports than write ports.
A typical prior art register file is arranged into rows and columns of static storage elements. Each static storage element stores a bit and is commonly implemented by connecting a pair of inverters together to form a feedback loop. Each row of storage elements forms a register of the register file. A row is also known in the art as a word. Each column of storage elements stores common bit positions of all the registers. For example, the first column may store bit
0
for each register.
For every row of the register file a word line is provided for each port. Typically the word lines run horizontally across the register file. For every column of the register file, a data line is provided for each port. Typically the data lines run vertically across the register file.
Consider a prior art register file having 128 64-bit registers, with twelve read ports and eight write ports. Such a register file will require 20 horizontal word lines for each register (twelve for the read ports and eight for the write ports) and 20 vertical data line for each bit position (again, twelve for the read ports and eight for the write ports). Accordingly, such a register will have 2560 horizontal word lines and 1280 vertical lines. The result is a register file completely dominated by wiring, which increases the size and complexity of the register file. As computer designers continue to increase the number of execution units in a processor, and therefore increase the number of ports in a register file, the problem will worsen. Accordingly, what is needed in the art is a register file configuration that reduces the number of lines required compared to prior art configurations, thereby allowing designers to continue to add ports to register files without being constrained by wiring.
SUMMARY OF THE INVENTION
The present invention is a multi-port computer register file having shared word lines for read and write ports and storage elements that power down or enter a high-impedance state during write operations. In accordance with the present invention, a register file has R read ports and W write ports. Typically, a register file will have more read ports than write ports, but the invention is not limited to this configuration.
Assume that a register file in accordance with the present invention has more read ports than write ports, as is common in the art. In such a register file, each register will be accessed by W combined read/write word lines, a single direction line, and R—W read-only word lines. The direction line is asserted during a write operation, and is not asserted during a read operation. A prior art register file would have R+W word lines. Therefore, if a register file has 12 read ports and 8 write ports, a prior art register file would have 20 horizontal lines for each register, while a register file in accordance with the present invention would have 13 horizontal lines for each register, which is a reduction of 35% in the number of horizontal word lines.
The direction line also allows the storage elements comprising a register to be powered down or enter a high-impedance state during a write operation. In the prior art, a typical storage element comprises a pair of inverters coupled into a feedback loop. During a write operation in a prior art register file, the output drivers of the write buffers overpower the output drivers of the storage elements, thereby causing the storage elements to assume the values provided by the write buffers. In the present invention, during a write operation the direction line is asserted and the storage elements are powered down or enter a high-impedance state. Therefore, the write buffers may be provided with smaller output drivers since they are not required to overpower the output drivers of the storage elements. When a write operation ends, the direction line is deasserted and the storage elements are powered up or leave the high-impedance state, thereby retaining the value provided by the write buffers. The direction line is also used as a multiplexer signal to enable the write operation at the write port represented by the combined read/write word line.
During a read operation, the direction line remains deasserted and the storage elements remain powered up and are not in a high-impedance state. For read ports sharing combined read/write word lines with write ports, the direction line is used as a multiplexer signal to enable a read operation at the read port represented by the combined read/write word line. For read ports that are not shared, a read-only word line is used to enable the read operation.
For a register file having an equal number of read and write ports, all ports are accessed using combined read/write word lines. For a register file have more write ports than read ports, all read ports and a number of write ports equal to the number of read ports are accessed using combined read/write word lines. Write ports in excess of the number of read ports are accessed using write-only word lines.
The present invention provides two important benefits over the prior art. First, by powering down storage elements or allowing storage elements to enter a high-impedance state during a write operation, smaller transistors can be used to write values into storage elements. By using smaller transistors, the size and power requirements of the register file are reduced. Second, by using a direction line and combined word lines for read and write ports, the number of horizontal lines running across the register file are reduced. Accordingly, the present invention provides a computer designer with the ability to implement a register file having a large number of read and write ports, while reducing the number of horizontal lines and reducing the size of output driver transistors used during write operations compared to prior art register file configurations.
REFERENCES:
patent: 5315178 (1994-05-01), Snider
patent: 5321652 (1994-06-01), Ito
patent: 5481495 (1996-01-01), Henkel et al.
patent: 5724299 (1998-03-01), Podlesny et al.
Auduong Gene N.
Hewlett--Packard Company
Nelms David
Plettner David A.
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