Method for growing field oxide to minimize birds' beak...

Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Recessed oxide by localized oxidation

Reexamination Certificate

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C438S439000, C438S452000, C438S450000

Reexamination Certificate

active

06333243

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to methods for manufacturing semiconductor devices, and in particular for achieving a thick field oxide with a minimum “birds' beak” length.
BACKGROUND OF THE INVENTION
Field oxide layers electrically isolate semiconductor devices from one another. The most common technique for their formation is termed LOCOS isolation (for LOCal Oxidation of Silicon). Silicon dioxide (SiO
2
) is formed on silicon surfaces through a process termed oxidation. In the formation of field oxides, SiO
2
, is thermally grown to thicknesses of between 3,000 to 10,000 angstroms. Usually, oxidation is accomplished by exposing the silicon to an oxidant ambient, such as oxygen (O
2
) or water (H
2
O), at elevated temperatures. Oxide is formed on those areas which are not covered by an oxidation mask, such as silicon nitride.
Silicon nitride is deposited by chemical vapor deposition (CVD), and photolithographically patterned to form the oxidation mask, using a dry etch. Silicon nitride is an effective mask due to the slow speed with which oxygen and water vapor diffuse in the nitride (typically only a few tens of nanometers of nitride are converted to SiO
2
during the field oxide growth process). Therefore, the nitride layer thickness is selected according to the time needed for the field oxidation step. Typically, the nitride masking layer is deposited to a thickness of between 1,000 and 2,000 angstroms. After field oxidation, the masking layer is removed by a wet etch for subsequent device formation in the regions previously under the mask.
Field oxide layers function to prevent parasitic conditions between devices, such as punchthrough. Although punchthrough can be reduced by separating devices by adequate distances, field oxide layers are important in that they help to decrease this distance, by providing an electrical isolation layer. This is of great concern, especially in the manufacture of ultra large scale integrated (ULSI) circuits, where attempts are made to achieve semiconductor chips of maximum density mainly by scaling down line widths to make them narrower. Scaling down facilitates formation of leakage current paths, causing unwanted DC power dissipation, noise margin degradation, and voltage shift on a dynamic mode. Adequate electrical isolation between devices is necessary to prevent such problems.
Although field oxide layers presently provide many advantages in semiconductor technology, there are several problems created by their application to a ULSI circuit die, including “birds' beak” formation, as indicated in
FIG. 1
at
110
. Lateral oxidation from encroachment, or growth of oxide under the nitride edge
112
, lifts the nitride layer
112
as it grows. This encroachment of the oxide between the nitride layer and the silicon substrate
114
forms a “birds' beak” structure
110
, termed due to its slowly tapered shape. The effect from the “birds' beak” structure
110
is often called the narrow width effect. In order to minimize the “birds' beak” structure
110
, a shorter oxidation time is required. When a short oxidation is used, the field oxide
116
thickness is reduced and the isolation properties for devices with small isolation are degraded. This effect limits the total number of devices that can be fit onto a single integrated circuit chip. A novel approach is required to apply the LOCOS process to ULSI circuits.
Another problem associated with the “birds' beak” structure is encountered during a later step of connecting metal to the source and drain regions of a MOS device. Any overetching during formation of the metal contact opening may expose the substrate regions under the source or drain region, shorting the device.
One approach to solving the problem of decreasing the “birds' beak” is to increase the H
2
/O
2
ratio during wet oxidation. Another approach is high pressure oxidation. Another prior art method employs the use of sidewall spacers to minimize the “birds' beak” phenomenon, such as shown in U.S. Pat. No. 5,393,693 to Ko et al.
Ko et al. utilize SiO
2
spacers in the nitride layer opening in conjunction with several other processing techniques. The spacers act as lateral oxidation inhibitors. Oxygen implantation is employed as one of several complex steps taught by the '693 patent. Prior to oxygen implantation, the '693 patent requires etching a region of the silicon substrate to a depth of between 2,000 and 5,000 angstroms. In addition, oxidation is performed following deposition of a polysilicon layer, through which oxygen can diffuse, during oxidation in a non-oxidant, nitrogen ambient. The use of spacers does not lend itself well to reducing line widths, and is just one of several steps required to minimize the birds' beak effect.
There is a need for an effective method to minimize the “birds' beak” phenomenon, which results during growth of field oxide, utilizing fewer, less complicated steps and providing thermal cost saving steps. As devices get smaller, and more devices must be fit on each chip, any waste of precious chip space is very costly. Narrower line widths also reduce the density of oxidants available in openings in the nitride layer and hence make it difficult to obtain thick oxide growth. There is a need to minimize the encroachment of field oxide under nitride layers, to allow an increase in chip density. There is also a need to reduce the time required for thermal oxidation while still obtaining thick oxide growth.
SUMMARY OF THE INVENTION
A method of forming a field oxide in a semiconductor device produces minimal encroachment under a patterned oxidation resistant structure. The oxide is formed by oxygen implantation in conjunction with a subsequent anneal in an oxidant atmosphere. The reduction of encroachment uses fewer steps than prior art methods of enhancing oxygen implantation, resulting in a lower thermal budget. Less encroachment also allows closer spacing of semiconductor structures, permitting increased chip density.
In one embodiment of the invention, deposition of a silicon nitride mask layer is followed by an oxygen implant. The oxygen implant is followed by the growth of oxide on the exposed substrate. Very little oxide encroachment is seen as a result of this method. To further enhance the rate of oxidation, an oxidant ambient at a pressure of between approximately 4×10
3
to 20×10
3
Torr is used.
In a second embodiment of the invention, deposition of the silicon nitride mask layer is followed by thermal oxide growth on the exposed substrate. This is followed by an oxygen implant, through the oxide, into the underlying silicon. The wafers are then annealed to form field oxide of the desired thickness.
An additional benefit of the present invention is that field oxide is formed without added steps of etching the silicon substrate and deposition of a polysilicon layer; as done in prior art methods. A polysilicon layer is not needed to increase the rate of oxidation in the present invention because an oxidant ambient is used during the oxidation step. The oxidant ambient and the implanted oxygen provide two sources of oxygen, originating from both sides of the desired field oxide area, as compared with prior art techniques of providing the oxygen source solely from the oxygen implant area Thus, the need for a polysilicon layer in the desired field oxide area has been removed.
By utilizing implantation of oxygen, this invention also helps to combat the oxide field-thinning effect In submicron-isolation, field oxide thickness has typically been significantly less than the thickness of field oxides grown in wider spacings. In the present invention, the field-thining effect is decreased due to an increase in the concentration of oxidants available in the opening, resulting from implantation of oxygen.


REFERENCES:
patent: 4372033 (1983-02-01), Chiao
patent: 4398992 (1983-08-01), Fang et al.
patent: 4523213 (1985-06-01), Konaka et al.
patent: 5182226 (1993-01-01), Jang
patent: 5236862 (1993-08-01), Pfiester

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