Semiconductor memory device enabling direct current voltage...

Details Semiconductor memory device enabling direct current voltage... Semiconductor memory device enabling direct current voltage...

1996-04-23

2001-10-02

Nguyen, Viet Q. (Department: 2511)

Static information storage and retrieval

Powering

C307S064000, C327S530000, C324S765010

Reexamination Certificate

active

06298001

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device. More particularly the present invention relates to a semiconductor memory device that allows for a direct current (DC) voltage test after packaging.
Recently, semiconductor memory devices have been designed to provide higher integration, multiple functions, and lower power dissipation. In response to these trends, the number of bonding pads
20
used to control a semiconductor device
15
have increased, as shown in FIG.
1
. This larger number of bonding pads
20
allows for high integration and multiple input and output functions. In addition to an increase in the number of bonding pads
20
, the number of DC voltage generators
10
of differing voltage levels in the semiconductor device
15
has also increased, resulting in an increase in the number of checking pads
22
required to check the voltage levels of these voltage generators. These DC voltage generators
10
are required for controlling power in the semiconductor device
15
, but the addition of the checking pads
22
serves to undesirably increase the chip size.
The checking pads
22
can be used to perform electrical tests regarding the status of the semiconductor deceive
15
when they are linked to probes connected to electrical test equipment. However, the DC voltage level of each checking pad
22
cannot be measured before the checking pads
22
are bonded with package leads, and so cannot be measured until the wafer assembly of the semiconductor device
15
is completed. As a result, it is extremely difficult, if not impossible, to find out how the assembly process in particular impacts on the DC voltage levels measured once the wafer is fully assembled.
Furthermore, the addition of more checking pads
22
to measure the DC voltage of the packaged semiconductor device
15
entails an undesirable increase in chip size and cost.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a semiconductor memory device for which a DC voltage test is possible even when in package form.
To achieve the above object, there is provided a semiconductor memory device comprising [claim
1
]
According to the present invention, as set forth in the appended claims, many types of DC voltage tests can be performed without an increase in chip size, since a general control pad serves also as a DC voltage test pad.


REFERENCES:
patent: 5251179 (1993-10-01), Wittman
patent: 5280455 (1994-01-01), Kanaishi
patent: 5297097 (1994-03-01), Etoh et al.
patent: 5446408 (1995-08-01), Tedrow et al.
patent: 5594360 (1997-01-01), Wojciechowski
patent: 5602794 (1997-02-01), Javanifard et al.
patent: 4-258893 (1992-09-01), None
patent: 4-258893 (1993-09-01), None

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