Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
1999-12-16
2001-02-20
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S063000
Reexamination Certificate
active
06191983
ABSTRACT:
BACKGROUND OF THE INVENTION
1.Field of the Invention
The present invention relates to a technology of highly integrated semiconductor memory and more specifically to a technology effectively applied to the disposition of a redundant memory cell and to a layout method of word drivers and sense amplifiers connected to the redundant memory cell.
2. Description of the Related Art
In the field of highly integrated semiconductor memories examined by the inventor, a technology of having a small number of redundant memory cells in addition to normal memory cells and of switching an access to the redundant memory cell when the normal memory cell is defective is widely used in order to improve the production yield.
As for the semiconductor memory having the redundant memory cells in addition to the normal memory cells as described above, there is a technology described in Japanese Patent Publication No. 2555252 entitled “Semiconductor Memory Device” for example. According to this technology, column redundancy is implemented by having a normal memory cell array and a redundant memory cell array in which a plurality of normal memory cell array blocks and a plurality of redundant memory cell array blocks are controlled in common by respective column decoders.
Noticing on the high integration of the semiconductor memory having the redundant memory cells in addition to the normal memory cells as described above, the inventor examined the disposition of the redundant memory cell and the layout method of word drivers and sense amplifiers connected to the redundant memory cell. The contents examined by the inventor will be explained below by using FIG.
10
.
FIG. 10
shows the disposition of the redundant memory cell. This redundant memory cell is positioned at the peripheral part of a normal memory cell array
15
as shown in FIG.
10
(
a
). Further, sense amplifier regions
16
, sub-word driver regions
17
and their intersection regions
18
are disposed adjacent to and around the memory cell array
15
as shown in FIG.
10
(
b
).
By the way, with the high integration of the semiconductor memory, while the plane size of the memory cell may be refined further by forming it in 3-D, direct peripheral circuits such as the word drivers and sense amplifiers connected with the memory cell must be reduced in the plane direction in correspondence to the memory cell. However, their layout is not easy because they are different from the memory cell and cannot be formed in 3-D.
Then, as a countermeasure thereof, there has been widely used a method of reducing an occupied area by sharing contacts, through holes, power sources and signal lines in a plurality of units of those circuits in a repeating pitch in which a plurality of memory cells are put together. For instance, it has been applied in the layout unit of word drivers corresponding to 16 word lines W and in the layout unit of sense amplifiers corresponding to 16 bit lines BL.
Meanwhile, along with the high integration of the memory, the yield of the redundant memory cell has also become a problem. Then, the redundant memory cell is disposed at the center of an array where the manufacturing condition is stable to make it alive. Because its test before setting a fuse may be eliminated or may be simplified if the redundant memory cell is surely alive, the whole test time may be shortened.
However, it has been difficult to lay out only the sub-word drivers or sense amplifiers related to the redundant memory cell specially because the number of word lines or bit lines of the redundant memory cell is smaller than the layout units. It is because the layout unit is too small so that the contacts, through holes, power sources and signal lines cannot be shared as described above. Further, there has been a possibility that the characteristics and yield of the sub-word drivers or sense amplifiers for the redundant memory cell become abnormal if the repeated shapes are different.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention to provide a semiconductor memory which allows a redundant memory cell to be disposed at the center while maintaining the continuity of layout units of direct peripheral circuits and allows the total yield of the memory cell and the direct peripheral circuits to be improved by an efficient layout method of sub-word drivers and sense amplifiers for disposing the redundant memory cell at the center of a memory cell array.
The above-mentioned and other objects and the novel characteristics of the invention will be apparent from the following description and the accompanying drawings.
The summary of the typical one of the inventions disclosed in the present specification will explained below briefly.
The inventive semiconductor memory is arranged such that even if a redundant memory cell is disposed at the center of a memory cell array, the same layout unit with the normal memory cell is used for the layout of sub-word drivers and sense amplifiers and the sub-word drivers and sense amplifiers which are increased due to the redundant memory cell is adjusted by a related circuit of the normal memory cell at the end of the memory cell array while maintaining the same repetition. Further, the changing point of the redundant memory cell and the normal memory cell is realized by replacing a control signal of the sub-word drivers and sense amplifiers.
This method allows the redundant memory cell to be disposed at the center while maintaining the continuity of the layout units of the direct peripheral circuits and the general yield of the memory cells and direct peripheral circuits to be improved. Further, it allows the defective occurrence rate to be reduced and the quality of the redundant memory cell to be improved as compared to the case of disposing the redundant memory cell at the peripheral part.
The effects obtained by the typical one of the inventions disclosed in the present specification will be explained below briefly.
(1) The quality of the redundant memory cell may be improved in the manufacturing process of the semiconductor memory by disposing the redundant memory cell approximately at the center of the word line and bit line directions of the memory cell array;
(2) The production yield of the memory cells and direct peripheral circuits may be improved because it is possible to maintain the normal repetition of the layouts of the direct peripheral circuits such as the sub-word drivers and sense amplifiers adjacent to the memory cell even when the redundant memory cell is disposed at the center; and
(3) The general yield in the layout of the highly integrated semiconductor memory may be improved and the total chip cost may be reduced including testing time by the effects (1) and (2).
The above-mentioned and other objects and the novel characteristics of the invention will be apparent from the following description and the accompanying drawings.
REFERENCES:
patent: 5673227 (1997-09-01), Engles et al.
patent: 5841961 (1998-11-01), Kozaru et al.
patent: 6-76594 (1994-03-01), None
patent: 8-55494 (1996-02-01), None
patent: 8-153399 (1996-06-01), None
patent: 2555252 (1996-08-01), None
Ishimatsu Manabu
Kitsukawa Goro
Mishima Michihiro
Ueda Toshitsugu
Antonelli Terry Stout & Kraus LLP
Hitachi , Ltd.
Nguyen Tan T.
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