Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
1999-12-29
2001-05-29
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S112000, C326S119000
Reexamination Certificate
active
06239621
ABSTRACT:
BACKGROUND
The present invention relates to a reset controller for a domino circuit characterized by improved turn off times.
As is known, integrated circuits may include domino circuits that carry active data on only one phase of a driving clock, called the “evaluation phase.” During another phase of the clock, the “precharging phase,” the domino circuit precharges its output to a predetermined value. A reset circuit in the domino circuit controls the precharging.
An evaluation circuit also is coupled to the output terminal having a data input terminal. If active data is input to the evaluation circuit during the evaluation phase, the evaluation circuit may drive the output terminal from the precharge voltage. The active data typically is removed from the evaluation circuit prior to the precharge phase. The reset circuit precharges the output terminal in preparation for another evaluation phase.
Known reset circuits may include a propagation path that extends from the output terminal to a precharge transistor. An output of the reset circuit drives the gate of the precharge transistor. Such reset circuits typically are characterized by a propagation delay that is sufficient to guarantee that the reset circuit will not cause the precharge transistor to precharge the output terminal at the same time that the evaluation terminal causes the output terminal to be driven to a different potential. If two transistors were permitted to drive the same terminal to two different potentials, it would cause contention and damage to the circuit. Thus, the delay of the reset circuit typically is designed to be large enough so that the precharge transistor is turned on only after the data signal that is input to the evaluation circuit is deactivated.
In known self-resetting domino circuits, the reset circuit that turns on the precharge transistor also turns it off. Thus, after the precharge circuit is activated, it remains activated for the same propagation delay that was designed into the reset circuit to avoid contention.
This feature of reset circuits may be disadvantageous. Although a relatively long delay in turning the precharge transistor on may be necessary to avoid contention at the output terminal, a long delay in turning off the precharge transistor is not necessary. An output terminal may be precharged very quickly relative to the length of the data pulse input to the domino circuit. No known reset circuit provides a different delay for activating a precharge transistor than for deactivating a precharge transistor.
Accordingly, there is a need in the art for a reset circuit in a domino circuit that provides activates a precharge transistor after a first delay but deactivates the precharge transistor after a second, shorter delay.
SUMMARY
According to an embodiment, the present invention provides a method of precharging a node in an integrated circuit in which the node is precharged a first predetermined delay after the node evaluates and, thereafter, the precharge ceases after a second shorter predetermined delay.
REFERENCES:
patent: 5543735 (1996-08-01), Lo
patent: 5550490 (1996-08-01), Durham et al.
patent: 5724249 (1998-03-01), Kodali et al.
Milshtein Mark S.
Sprague Milo D.
Intel Corporation
Kenyon & Kenyon
Le Don Phu
Tokar Michael
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