Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1998-05-28
2001-02-27
De Cady, Albert (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
Reexamination Certificate
active
06195782
ABSTRACT:
FIELD OF THE INVENTION
This invention is related to the field of channel equalization in the context of cellular radio communication, and particularly to a combined hardware and software MLSE equalizer structure in the GSM cellular radio system.
DESCRIPTION OF THE RELATED ART
In the GSM cellular radio system, base stations and mobile units transmit and receive digitized voice data in the 900 MHz band. The 890-915 MHz band is reserved for mobile-to-base transmissions (up link), and the 935-960 MHz band is reserved for base-to-mobile transmissions (down link). These bands are divided into channels which are 200 kHz wide. A pair of channels, an up link channel and a down link channel, separated by 45 MHz is described by an Absolute Radio Frequency Channel Number (ARFCN). In normal communications each mobile unit is assigned an ARFCN, asserting its transmissions over the up link channel, and receiving base station transmissions over the down link channel.
Each base station is capable of operating over several ARFCNs. Furthermore, on each ARFCN the base station may be in contact with up to eight mobile units. The mobile units share an ARFCN by a scheme of Time-Division Multiple Access (TDMA), wherein communications over the up link and down link channels are divided into frames, and each frame is further sub-divided into eight time-slots. Each of the eight mobile units is assigned a time-slot number and is expected to confine its transmissions on the up link channel to the corresponding time-slot, and to receive down-link transmissions in the corresponding time-slot. Thus the GSM transmitter (base or mobile) must assemble speech data into bursts (of length 148 bits). When asserting the burst during a time-slot, the transmitter shapes the power envelope of the transmitter RF signal in conformity with a GSM power-ramping time-mask. The power envelope is used by the receiver (base or mobile) to detect the start of the burst and to synchronize its A/D sampling.
The GSM transmitter uses the Gaussian Minimum-Shift Keying (GMSK) modulation technique, in which the binary speech data is embedded onto a baseband signal that modulates the carrier with a bit rate of 270833 bits per second. The modulated carrier is transmitted into the atmosphere as an RF signal. The receiver accepts the RF signal from the atmosphere, and down-converts this RF signal to produce a baseband signal. Due to the effects of the atmosphere or transmission channel, the received baseband signal is a distorted version of the transmitted baseband signal. The distortions include atmospheric channel fading, multipath, noise, and the distortions imposed by the RF stages of the transmitter and receiver.
A typical GSM receiver structure includes: an RF stage which converts the received RF signal into a baseband signal; an analog-to-digital (A/D) converter which samples the baseband signal at a rate of 270833 samples per second, i.e. once per bit interval, to produce a sequence of received samples; a channel estimator which estimates parameters describing the transmission channel on a burst by burst basis; and a Viterbi equalizer which uses the channel parameters to demodulate the binary speech data from the A/D samples.
In the 900 MHz band transmissions are subject to channel fading and multipath, which results in significant inter-symbol interference (ISI). Furthermore, the RF stages of the transmitter and the receiver are non-ideal, and exhibit their own transfer characteristics. The channel estimator is designed to estimate parameters which describe the transmission channel, i.e. estimate the transfer function of the transmission channel. In this application, the transmission channel is interpreted to include one or more (preferably all) of the signal stages between the transmitted baseband and received baseband signals. Thus the transmission channel includes one or more of the following: the RF stage of the transmitter, the atmospheric medium, and the RF stage of the receiver. The channel estimator assumes that the transmission channel can be modeled as a discrete-time linear system, and calculates the impulse response of this linear model.
To facilitate the estimation procedure for the transmission channel impulse response, each transmitted burst contains known training data. In particular, every burst, which comprises 148 successive bits, contains a training sequence of length 26 bits. The channel estimator uses the samples of the received burst and the known training sequence in its estimation algorithm. The Viterbi equalizer uses the transmission channel impulse response, i.e. the transfer function calculated by the channel estimator, to process the received samples and compensate for the ISI. In doing so, the Viterbi equalizer demodulates the encoded binary speech data.
The GSM Specification imposes a limit on the bit error rate (BER) of a GSM receiver with the constraint of a five-tap complex channel model. In order to reduce the effect of ISI on symbol detection, GSM receivers typically use a Viterbi Decoder based on a Maximum Likelihood Sequence Estimation criteria. However, the complexity of the MLSE algorithm imposes a significant computational burden on the equalizer. Thus, an MLSE Equalizer is not always realizable in terms of software running on a general purpose digital signal processor (DSP). Thus, it is desirable to investigate the possibility of partitioning the MLSE equalizer computations between a general purpose DSP and specialized hardware.
SUMMARY OF THE INVENTION
The present invention comprises a composite software and hardware system for decoding a sequence of symbols embedded in a received baseband signal. The hardware module is optimized to perform calculations in the decoding algorithm which are computationally intensive and repetitive in nature. The software module running on a general purpose digital signal processor (DSP) pre-calculates parameters used by the hardware module, and interprets the results produced by the hardware module. Thus, the present invention may advantageously achieve an optimal distribution of processing tasks between the software module and hardware module to maximize the efficiency and accuracy of the decoding algorithm.
In the preferred embodiment of the present invention, the baseband signal is supplied to a sampling device such as an A/D Converter. The sampling device produces a sequence of received samples from the baseband signal. A general purpose digital signal processor (DSP) calculates a set of channel coefficients based on portion of the symbol sequence which are known apriori. For example, in the GSM signaling standard, the mid-amble bits are predetermined and are designed to facilitate channel estimation.
After the channel coefficients become available, the DSP calculates a plurality of combination values associated with a state space. A state comprises an ordered collection of four symbol values. One combination value is calculated for each possible state. A combination represents the effect of an assumed past history on a candidate sample value. Furthermore, the DSP calculates a plurality of branch product values. The branch product values represent the effect of an assumed current symbol on the candidate sample value. The combination value and branch products values are stored into shared memory for later use by a hardware module. The hardware module is specialized to perform all the calculations associated with one stage of the Viterbi algorithm. However, before the hardware module can be invoked, a path metric value must be defined for each state in the state space. Thus, the DSP performs the first few stages of the Viterbi algorithm so that each state is assigned a well-defined path metric value. The DSP also loads the computed error values for each state into shared memory.
The DSP invokes the hardware module by writing a received sample to the hardware module. In response to the received sample, the hardware module accesses the shared memory for combination values, branch product values, and error values, and performs the calculations associated wit
Rahmatullah Muhammad M.
Sawan Tony E.
Yip Philip
Advanced Micro Devices , Inc.
Cady Albert De
Chase Shelly A
Conley Rose & Tayon
Hood Jeffrey C.
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