Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
1999-07-29
2001-05-29
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S723000, C257S737000, C257S685000, C257S686000
Reexamination Certificate
active
06239495
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a multichip semiconductor device and a memory card, and more specifically, a multichip semiconductor device and a memory card on which a plurality of semiconductor memory chips or a plurality of semiconductor chips formed in both semiconductor memories and logic circuits are mounted in layers.
There has been a rapidly increasing demand for memory cards used as film media of digital cameras or storage devices of mobile personal computers. For example, an SSFDC (Solid-State Floppy Disk Card) mounted on a non-volatile memory, e.g., a NAND-type EEPROM, is known as a kind of memory card, so-called “Smart Media”. A memory card on the market at present contains a 16-Mbit or 32-Mbit NAND-type EEPROM and has a memory capacity of 2 Mbytes or 4 Mbytes. However, due to the recent multimedia boom, it is expected that the demand for memory cards with a larger capacity will be much increased. For example, as regards a current digital camera, images corresponding to 30 pictures of 300,000 pixels can be recorded on a card of 2 Mbytes. However, to record 30 pictures with a camera capable of processing an image of 1.3 million pixels, a memory capacity of 8 Mbytes is required. Further, the use of the memory card is to record not only static images but also dynamic images or audio signals. In the case of recording a dynamic image or an audio signal, a much larger memory capacity is required. Therefore, it is desirable that a plurality of semiconductor chips be mounted on a card to realize a large capacity.
However, according to the conventional art, to mount a plurality of semiconductor chips on a card, the card must inevitably be large. More specifically, if chips are arranged on the same plane, the area of the card must be increased. On the other hand, if chips are arranged on a plurality of layers to keep the area of the card small, the card must be thick.
To overcome this problem, the present applicant proposed an invention titled “Multichip Semiconductor Device and Chip for Use in Multichip Semiconductor Device, and Method for Manufacturing the Same” in Japanese Patent Application No. 8-321531 filed Dec. 2, 1996. According to this prior invention, a plurality of semiconductor chips are mounted on a card, the size of which is suppressed to the minimum. The application discloses a multichip semiconductor device comprising a plurality of chips each having a semiconductor substrate on which elements are integrated. The multichip semiconductor device is characterized in that at least one of the chips has a connecting plug inserted in a through hole made through the semiconductor substrate, and that said at least one chip having the plug is electrically connected to another chip.
The technique of the aforementioned multichip semiconductor device can provide a thin memory card which is small in area of the plane surface and simple in structure. However, some problems to be solved are left to realize a smaller memory card or memory device of a larger memory capacity. For example, it is assumed that four 64-Mbit semiconductor chips are used to constitute a 256-Mbit memory device. In this case, if the chips are mounted on a conventional plane board, chip enable bar signals ({overscore (CE)}), i.e., chip control signals for the four chips, may be individually supplied to the chips. However, if such a memory device is realized by the multichip semiconductor structure having chips laminated in layers, instead of the plane board, it is necessary to separate the four interconnection lines for the signals {overscore (CE)} from one another. This means that four kinds of chips A to D, to which signals {overscore (CE)} are input at different positions, are required. Four kinds of chips can be produced by four masks for patterning, for example, the uppermost wiring layers of the respective chips. The four kinds of chips may be stacked in a predetermined order, for example, A-B-C-D. However, in consideration of the production cost, this method is not preferable. More specifically, in this case, four kinds of chips must be produced, the produced chips must be tested, and they must be stacked in the predetermined order without fail. Therefore, the memory device comprising the four types of chips is inevitably more expensive than that in which four chips of the same kind are stacked.
As described above, the multichip semiconductor device or the memory card of the conventional art has a problem that it must be large in the case where a plurality of semiconductor chips are mounted.
The applicant of the present invention proposed one means for solving the problem in the aforementioned prior Japanese patent application. However, to realize a smaller memory card or memory device with a much greater memory capacity, a higher manufacturing cost is required.
BRIEF SUMMARY OF THE INVENTION
Accordingly, a first object of the present invention is to provide a thin multichip semiconductor device which is small in area of the plane surface and simple in structure without increasing the manufacturing cost.
A second object of the present invention is to provide a thin memory card which is small in area of the plane surface and simple in structure without increasing the manufacturing cost.
The first object of the present invention is achieved by a multichip semiconductor device comprising a plurality of semiconductor chips of substantially same structure stacked in layers, each semiconductor chip including: a semiconductor substrate and elements integrated therein; an option circuit formed in the semiconductor substrate; a connecting plug inserted in a through hole made through the semiconductor substrate; and a bump for selectively connecting the connecting plug in the semiconductor substrate, wherein the option circuits formed in the semiconductor chips are selected in accordance with a connecting pattern of the bumps.
With the above constitution, since a plurality of semiconductor chips of the same structure are stacked, it is unnecessary to produce a plurality of kinds of semiconductor chips of different structures, and all semiconductor chips can be subjected to the same test. Further, it is unnecessary to consider the order of semiconductor chips to be stacked. Therefore, the production cost can be reduced. In addition, the option circuits in the semiconductor chips can be suitably selected in accordance with the connecting pattern of the metal bumps between the stacked semiconductor chips. Further, if a plurality of semiconductor chips are stacked on a substrate, the option circuits can be suitably selected in accordance with the connecting pattern of the metal bumps between the stacked semiconductor chips and the connecting pattern of the metal bumps between the substrate and the lowermost semiconductor chip.
The first object of the present invention is also achieved by a multichip semiconductor device comprising a plurality of semiconductor chips of substantially same structure stacked in layers, each semiconductor chip including: a semiconductor substrate and elements integrated therein; a connecting plug inserted in a through hole made through the semiconductor substrate; and a bump for selectively connecting the connecting plug in the semiconductor substrate, wherein allocation of addresses of the semiconductor chips is designated by a connecting pattern of the bumps.
With the above constitution, since a plurality of semiconductor chips of the same structure are stacked, it is unnecessary to produce a plurality of kinds of semiconductor chips of different structures, and all semiconductor chips can be subjected to the same test. Further, it is unnecessary to consider the order of semiconductor chips to be stacked. Therefore, the production cost can be reduced. In addition, the allocation of the addresses of the semiconductor chips can be designated in accordance with the connecting pattern of the metal bumps between the stacked semiconductor memory chips.
The second object is achieved by a memory card comprising: a plurality of semiconductor memory chips of s
Hayasaka Nobuo
Miyamoto Junichi
Okumura Katsuya
Sakui Koji
Banner & Witcoff , Ltd.
Clark Jhihan B
Kabushiki Kaisha Toshiba
Lee Eddie C.
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